ICS844004-104 IDT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 16

Technical content

Features

  • Four differential LVDS outputs
  • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
  • Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
  • VCO range: 560MHz - 680MHz
  • RMS phase jitter at 212.5MHz (637kHz – 10MHz), using a 26.5625MHz crystal: <1ps (typical)
  • Full 3.3V or 2.5V output supply modes
  • 0°C to 70°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages

Table 1. Frequency Table

32 Lead VFQFN

Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, nQ0 Output Differential outp ut pair. LVDS interface levels.

3 MR Input Pulldown

to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 11 V DD Power Core supply pin. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 17, 22 GND Power Power supply ground. 18 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 23, 24 nQ3, Q3 Output Diffe rential output pair. LVDS interface levels. 25, 32 V DDO Power Output supply pins. 26, 27 Q2, nQ2 Output Differ ential output pair. LVDS interface levels. 30, 31 nQ1, Q1 Output Diffe rential output pair. LVDS interface levels.

FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 3 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 3B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 42.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 105 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 120 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.10 2.5 V DD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 100 mA

Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 5 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 35 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 212.5MHz, (637kHz - 10MHz) 0.73 ps 159.375MHz, (637kHz - 10MHz) 0.78 ps 106.25MHz, (637kHz -10MHz) 0.92 ps 53.125MHz, (637kHz - 10MHz) 0.95 ps 187.5MHz, (637kHz - 10MHz) 0.75 ps t R / tF Output Rise/Fall Time 20% to 80% 250 500 ps odc Output Duty Cycle Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 35 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 212.5MHz, (637kHz - 10MHz) 0.72 ps 159.375MHz, (637kHz - 10MHz) 0.88 ps 106.25MHz, (637kHz -10MHz) 0.89 ps 53.125MHz, (637kHz - 10MHz) 0.96 ps 187.5MHz, (637kHz - 10MHz) 0.74 ps t R / tF Output Rise/Fall Time 20% to 80% 250 550 ps odc Output Duty Cycle

FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 6 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 Typical Phase Noise at 106.25MHz (3.3V) Typical Phase Noise at 212.5MHz (3.3V) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 106.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.89ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.72ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 7 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Skew Output Rise/Fall Time 2.5V LVDS Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDD, VDDO VDDA tsk(o) Qx nQx Qy nQy VOS 20% 80% 80% 20% tR tF VOD GND nQ[0:3] QA[0:3} SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND LVDS VDD, VDDO VDDA Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ[0:3] QA[0:3} tPW tPERIOD tPW tPERIOD odc = x 100%

FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 8 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 Parameter Measurement Information, continued Differential Output Voltage Setup Offset Voltage Setup

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS844004-104 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering

recommend that there is no trace attached. matched load termination of 100Ω across near the receiver input. it is recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination

the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

This section provides information on power dissipation and junction temperature for the ICS844004-104. Equations and example calculations are also provided. load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 42.4°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN Table 9. Package Dimensions page. The package dimensions are in Table 8 below.

FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 15 ICS844004AK-104 REV. A SEPTEMBER 15, 2008

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT product for use in life support devices or critical medical instruments.

FEMTOCLOCK™CRYSTAL-TO-LV DS FREQUENCY SYNTHESIZER www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) Contact Information: www.IDT.com