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- PDF pages: 19
Technical content
Features
- Three LVDS outputs on two banks, Bank A with one LVDS pair and Bank B with 2 LVDS output pairs
- Using a 19.44MHz, 20MHz, or 25MHz crystal, the two output banks can be independently set for 625MHz, 622.08MHz, 312.5MHz, 250MHz, 156.25MHz, 125MHz or 100MHz
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
- VCO range: 490MHz to 680MHz
- RMS phase jitter at 125MHz (1.875MHz – 20MHz): 0.50ps (typical)
- Full 3.3V output supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- For functional replacement part use 8T49N241 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 GND XTAL_IN XTAL_OUT XTAL_SEL VCO_SEL MR GND nc QA0 nQA0 GND QB0 nQB0 QB1 nQB1 VDDO_B DIV_SELA1 DIV_SELA0 DIV_SELB1 DIV_SELB0 GND FB_DIV OEB OEA VDD nc nc VDDA VDD nc VDDO_A REF_CLK Phase Detector VCO 490-680MHz 0 = ÷25 (default) 1 = ÷32 0 0 ÷2 0 1 ÷4 (default) 1 0 ÷5 1 1 ÷8 FB_DIV OSC 0 0 ÷1 0 1 ÷2 (default) 1 0 ÷3 1 1 ÷4 QA0 nQA0 QB0 nQB0 QB1 nQB1 OEA DIV_SELA[1:0] DIV_SELB[1:0] FB_DIV MR OEB VCO_SEL XTAL_SEL REF_CLK XTAL_IN XTAL_OUT Pullup Pulldown:Pullup Pullup Pulldown Pullup Pulldown Pulldown:Pullup Pulldown Pullup Block Diagram Pin Assignment 844003I-04
32 Lead VFQFN
5mm x 5mm x 0.925mm package body K Package Top View 844003I-04 Datasheet FemtoClock® Crystal-to-LVDS Frequency Synthesizer
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 7, 13, 22 GND Power Power supply ground. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. single-ended reference clock.
4 XTAL_SEL Input Pullup
Crystal select pin. Selects between the single-ended REF_CLK or crystal interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels.
5 VCO_SEL Input Pullup
dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels.
6 MR Input Pulldown
resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. 8, 26, 29, 30 nc Unused No connect. 9 DIV_SELA1 Input Pulldown Division select pin for Bank A. Default = LOW. LVCMOS/LVTTL interface levels. 10 DIV_SELA0 Input Pullup Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels. 11 DIV_SELB1 Input Pulldown Division select pin for Bank B. Default = LOW. LVCMOS/LVTTL interface levels. 12 DIV_SELB0 Input Pullup Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels. 14 FB_DIV Input Pulldown Feedback divide select. When Low (default), the feedback divider is set for ÷25. When HIGH, the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels.
15 OEB Input Pullup
the outputs is enabled. LVCMOS/LVTTL interface levels.
16 OEA Input Pullup
the outputs is enabled. LVCMOS/LVTTL interface levels. DDO_B Power Output power supply pin for Bank B outputs. 18, 19 nQB1, QB1 Output Differential Bank B output pair. LVDS interface levels. 20, 21 nQB0, QB0 Output Differential Bank B output pair. LVDS interface levels. 23, 24 nQA0, QA0 Output Differential Bank A output pair. LVDS interface levels. 25 V DDO_A Power Output supply pin for Bank A outputs. 27, 31 V DD Power Core supply pins. 28 V DDA Power Analog supply pin.
32 REF_CLK Input Pulldown
Table 2. Pin Characteristics
0 High-Impedance
1 Active (default)
4©2016 Integrated Device Technology, Inc. Revision C, November 10, 2016 844003I-04 Datasheet Table 3F. Bank A Frequency Table Inputs Feedback Divider Bank A Output Divider M/N Multiplication Factor QA0, nQA0 Output Frequency (MHz) Crystal Frequency (MHz) FB_DIV DIV_SELA1 DIV_SELA0 25 0 0 0 25 2 12.5 312.5 20 0 0 0 25 2 12.5 250 25 0 0 1 25 4 6.25 156.25 24 0 0 1 25 4 6.25 150 20 0 0 1 25 4 6.25 125 25 0 1 0 25 5 5 125 25 0 1 1 25 8 3.125 78.125 24 0 1 1 25 8 3.125 75 20 0 1 1 25 8 3.125 62.5 19.44 1 0 0 32 2 16 311.04 15.625 1 0 0 32 2 16 250 19.44 1 0 1 32 4 8 155.52 18.75 1 0 1 32 4 8 150 15.625 1 0 1 32 4 8 125 15.625 1 1 0 32 5 6.4 100 19.44 1 1 1 32 8 4 77.76 18.75 1 1 1 32 8 4 75 15.625 1 1 1 32 8 4 62.5
5©2016 Integrated Device Technology, Inc. Revision C, November 10, 2016 844003I-04 Datasheet Table 3G. Bank B Frequency Table Inputs Feedback Divider Bank B Output Divider M/N Multiplication Factor QBx/ nQBx Output Frequency (MHz) Crystal Frequency (MHz) FB_DIV DIV_SELB1 DIV_SELB0 25 0 0 0 25 1 25 625 25 0 0 1 25 2 12.5 312.5 20 0 0 1 25 2 12.5 250 22.5 0 1 0 25 3 8.333 187.5 25 0 1 1 25 4 6.25 156.25 24 0 1 1 25 4 6.25 150 20 0 1 1 25 4 6.25 125 19.44 1 0 0 32 1 32 622.08 19.44 1 0 1 32 2 16 311.04 15.625 1 0 1 32 2 16 250 18.75 1 1 0 32 3 10.667 200 19.44 1 1 1 32 4 8 155.52 18.75 1 1 1 32 4 8 150 15.625 1 1 1 32 4 8 125
6©2016 Integrated Device Technology, Inc. Revision C, November 10, 2016 844003I-04 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 10%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 10%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.97 3.3 3.63 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDO_A, VDDO_B Output Supply Voltage 2.97 3.3 3.63 V IDD Power Supply Current 140 mA IDDA Analog Supply Current 20 mA IDDO_A + IDDO_B Output Supply Current 70 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_CLK, MR, FB_DIV, DIV_SELA1, DIV_SELB1 VDD = VIN = 3.63V 150 µA OEA, OEB, VCO_SEL, XTAL_SEL, DIV_SELB0, DIV_SELA0 VDD = VIN = 3.63V 5 µA IIL Input Low Current REF_CLK, MR, FB_DIV, DIV_SELA1, DIV_SELB1 VDD = 3.465V, VIN = 0V -5 µA OEA, OEB, VCO_SEL, XTAL_SEL, DIV_SELB0, DIV_SELA0 -150 µA
Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Characterized with DIV_SELA[1:0] = 11 and DIV_SELB[1:0] = 11. NOTE 5: Characterized with DIV_SELA[1:0] = 00 and DIV_SELB[1:0] = 00. NOTE 6: Please refer to the Phase Noise Plots.
9©2016 Integrated Device Technology, Inc. Revision C, November 10, 2016 844003I-04 Datasheet Typical Phase Noise at 100MHz Typical Phase Noise at 625MHz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.34ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
10©2016 Integrated Device Technology, Inc. Revision C, November 10, 2016 844003I-04 Datasheet Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Output Skew Output Rise/Fall Time RMS Phase Jitter Bank Skew Output Duty Cycle/Pulse Width/Period 3.3V ±5% VDD, VDDO_A, VDDAVDDO_B Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD nQA0, nQB[0:1] QA0, QB[0:1] Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power t sk(b) nQB0 QB0 nQB1 QB1 nQA0, nQB[0:1] QA0, QB[0:1]
resistance is not required but can be added for additional protection. resistor can be tied from the REF_CLK to ground. at the receiver and a 100 differential transmission line environment. Figure 4. Typical LVDS Driver Termination
and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Figure 6 shows an example of an 844003I-04 application schematic. without built-in termination are shown in this schematic. Figure 6. ICS870931I-01 Schematic Layout Example
10 QA0
This section provides information on power dissipation and junction temperature for the 844003I-04. Equations and example calculations are also provided. The total power dissipation for the 844003I-04 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (140mA + 20mA) = 580.80mW
- Power (outputs) MAX = VDDO_MAX * IDDO_MAX = 3.63V * 70mA = 254.1mW Total Power_MAX = 580.80mW + 254.1mW = 834.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.835W * 37°C/W = 115.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
18©2016 Integrated Device Technology, Inc. Revision C, November 10, 2016 844003I-04 Datasheet
32 Lead VFQFN Package Outline and Package Dimensions
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Te chnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
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Ordering Information
Table 10. Ordering Information Absolute Maximum Ratings - updated Input Ratings. DDO from 55mA max to 70mA max. AC Characteristics Table - corrected NOTES. Updated Overdriving the XTAL Interface application note. Updated LVDS Driver Termination application note. Updated Power Considerations to coincide with IDDO spec change. B 1 Product Discontinuation Notice - Last time buy expires November 2, 2016. T10 19 Obsolete datasheet per PDN# CQ-15-05. Ordering Information table - deleted Tape & Reel count and table note. Updated datasheet header/footer.