844003AGLF

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Technical content

Features

• Three LVDS outputs on two banks, A Bank with one LVDS pair and B Bank with two LVDS output pairs
• Using a 31.25MHz or 26.041666MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.63ps (typical)
• 3.3V output supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) packaging Block Diagram 1Phase DetectorOSC VCO 0 = ÷20 (default) 1 = ÷24 0 0 ÷1 0 1 ÷2 (default) 1 0 ÷4 1 1 ÷5 0 0 ÷1 0 1 ÷2 1 0 ÷4 (default) 1 1 ÷5 FB_DIV OEA Pullup Pulldown:Pullup Pullup Pulldown Pullup Pulldown Pullup:Pulldown Pulldown Pullup DIV_SELA[1:0] VCO_SEL TEST_CLK XTAL_IN XTAL_OUT XTAL_SEL FB_DIV DIV_SELB[1:0] MR OEB QA0 nQA0 QB0 nQB0 QB1 nQB1 DIV_SELB1 V DDO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT GND DIV_SELA1 DIV_SELB0 VCO_SEL MR V DDO_A QA0 nQA0 OEB OEA FB_DIV VDDA VDD DIV_SELA0 844003 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View Pin Assignment 844003 Datasheet FemtoClock® Crystal-to-3.3V LVDS Frequency Synthesizer

844003 Datasheet

Table 1. Pin Descriptions 1 DIV_SELB0 Input Pulldown Division select pin for Bank B. LVCMOS/LVTTL interface levels. See Table 3C.

2 VCO_SEL Input Pullup

dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels.

3 MR Input Pulldown

causing the true outputs Qx to go low and the inverted outputs nQx to go high. are enabled. LVCMOS/LVTTL interface levels. 4V DDO_A Power Output supply pin for Bank A outputs. 5 QA0 Output Differential output pair. LVDS interface levels. 6 nQA0 Output Differential output pair. LVDS interface levels.

7 OEB Input Pullup

state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3F.

8 OEA Input Pullup

output is enabled. LVCMOS/LVTTL interface levels. See Table 3E.

9 FB_DIV Input Pulldown

Feedback divide select. When Low (default), the feedback divider is set for ÷20. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 11 V DD Power Core supply pin. 12 DIV_SELA0 Input Pullup Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C. 13 DIV_SELA1 Input Pulldown Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C. 14 GND Power Power supply ground. 15 XTAL_OUT Output Parallel resonant cryst al interface. XTAL_OUT is the output.

16 XTAL_IN Input

17 TEST_CLK Input Pulldown

low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels.

18 XTAL_SEL Input Pullup

default. LVCMOS/LVTTL interface levels. 19 nQB1 Output Differential output pair. LVDS interface levels. 20 QB1 Output Differential output pair. LVDS interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 21 nQB0 Output Differential output pair. LVDS interface levels. 22 QB0 Output Differential output pair. LVDS interface levels. 23 V DDO_B Power Output supply pin for Bank B outputs. 24 DIV_SELB1 Input Pullup Division select pin for Bank B. LVCMOS/LVTTL interface levels. See Table 3C.

4©2016 Integrated Device Technology, Inc. January 29, 2016 Table 3A. Bank A Frequency Table 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Table 3B. Bank B Frequency Table 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Inputs Feedba ck Divider Bank A Output Divider M/N Multiplicatio n Factor QA0, nQA0 Output Frequency (MHz) Crystal Frequency (MHz) DIV_SELA1 DIV_SELA0 FB_DIV Inputs Feedback Divider Bank B Output Divider M/N Multiplicatio n Factor QB[1:0], nQB[1:0] Output Frequency (MHz) Crystal Frequency (MHz) DIV_SELB1 DIV_SELB0 FB_DIV

5©2016 Integrated Device Technology, Inc. January 29, 2016 Table 3C. Output Bank Configuration Select Function Table 0 0 ÷1 0 0 ÷1 0 1 ÷2 0 1 ÷2 1 0 ÷4 1 0 ÷4 1 1 ÷5 1 1 ÷5 Table 3D. Feedback Divider Configuration Select Function Table 0 ÷20 1 ÷24 Table 3E. OEA Select Function Table Table 3F. OEB Select Function Table

0 High-Impedance High-Impedance 0 High-Impedance High-Impedance

1 Active Active 1 Active Active

Inputs Outputs Inputs Outputs DIV_SELA1 DIV_SELA0 QA DIV_SELB1 DIV_SELB0 QB Inputs FB_DIV Feedback Divide Inputs Outputs Inputs Outputs OEA QA0 nQA0 OEB QB[1:0] nQB[1:0]

6©2016 Integrated Device Technology, Inc. January 29, 2016 Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO  Continuous Current 10mA  Surge Current 15mA Package Thermal Impedance, JA 78°C/W (1m/s airflow) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS / LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO_A, B Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 99 mA IDDA Analog Supply Current 10 mA IDDO_A + IDDO_B Output Supply Current 52 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current TEST_CLK, MR, FB_DIV, DIV_SELA1, DIV_SELB0 VDD = VIN = 3.465V 150 A DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, OEA, OEB V DD = VIN = 3.465V 5 A IIL Input Low Current TEST_CLK, MR, FB_DIV, DIV_SELA1, DIV_SELB0 VDD = 3.465V, VIN = 0V -5 A DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, OEA, OEB V DD = 3.465V, VIN = 0V -150 A

Table 5. Crystal Characteristics

Table 6. AC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

9©2016 Integrated Device Technology, Inc. January 29, 2016 Typical Phase Noise at 156.25MHz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 Noise Power (dBc/Hz) 100 1k 10k 100k Offset Frequency (Hz) 1M 10M 100M 10GB Ethernet Filter Raw Phase Noise Data Phase Noise result by adding 10Gb Ethernet Filter to raw data 156.25MHz, RMS Phase Jitter (Random), 1.875MHz to 20MHz = 0.63ps

10©2016 Integrated Device Technology, Inc. January 29, 2016 Recommendations for Unused Input and Output Pins Inputs: Crystal Input: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK Input: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.

11©2016 Integrated Device Technology, Inc. January 29, 2016 Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50  applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface VCC XTAL_OUT XTAL_IN 100 100 Zo = 50 ohmsRsRo Zo = Ro + Rs .1uf LVCMOS Driver XTAL_OU T XTAL_I N Zo = 50 ohms C2 .1uf LVPECL Driver Zo = 50 ohms 50R3

12©2016 Integrated Device Technology, Inc. January 29, 2016 For a general LVDS interface, the recommended value for the termi- nation impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmis- sion-line environment. In order to avoid any transmission-line reflec- tion issues, the components should be surface mounted and must be pla ced as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 2A can be used with either type of output structure. Figure 2B, which can also be used with both output types, is an op- tional termination with center tap capaci tance to help filter common mode noise. The capacitor value should be approximately 50pF . If us- ing a non-standard termination, it is recommend ed to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be veri- fied for compatibility with the output. LVDS Driver LVDS Driver LVDS Receiver LVDS ReceiverZT C ZO  ZT ZO  ZT ZT ZT Figure 2A. Standard Termination Figure 2B. Optional Termination LVDS Termination

13©2016 Integrated Device Technology, Inc. January 29, 2016 Figure 3 shows an example 844003 application schematic. The sche- matic example focuses on functional connections and is not configu- ration specific with the exception of the selection of the 31.25MHz crystal frequency. This decision requires that FB_DIV = 0. If a 26.041666MHz crystal had been selected, then FB_DIV = 1. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. Input and output terminations shown are intended as examples only and may not represent the ex act user configuration. In this example an 18pF parallel resonant 31.25MHz crystal is used with load caps C4 = C5 = 22pF . The load caps shown were used to tune the IDT device characterization board and are recommended for frequency accuracy, but these may be adjusted for different board layouts. Crystals with different load capacities may be used, but the load capacitors will have to be changed accordingly. If different crys tal types are used, please consult IDT for recommendations. The schematic example shows two different LVDS output termina- tions; the standard termination 100 shunt termination for an LVDS compliant receiver and an ac coupled termination for a non- LVDS dif- ferential receiver. The ac coupled termination requires that the de- signer select the values of R4 and R5 in order to center the LVDS swing within the common mode range of the receiver. In addition the designer must make sure that the target receiver will operate reliably with the LVDS swing, which is reduced relative to other logic families such as HCSL or LVPECL. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 844003 provides separate VDD, VDDA, VDDO_A and VDDO_B pins to isolate any high speed switching noise at the outputs from coupling into the internal PLL. In order to achieve the best possible filtering, it is highly recommend- ed that the 0.1µF capacitors be placed on the 844003 side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite beads, 10uf capacitors and the 0.1uF capacitors connect- ed directly to 3.3V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component val ues be adjusted and if required, additional filtering be added. Addi- tionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all de vices.

7 OEA

Figure 3. 844003 Application Schematic

Equations and example calculations are also provided. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum recommended junction temperature is 125°C. and a multi-layer board, the appropriate value is 78°C/W per Table 7 below. Table 7. Thermal Resistance JA for 24-lead TSSOP Package

Table 8. JA vs. Air Flow Table for a 24-lead TSSOP

17©2016 Integrated Device Technology, Inc. January 29, 2016

Ordering Information

Table 10. Ordering Information

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