ICS844002I-01 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Two differential LVDS outputs
  • Selectable crystal oscillator interface or single-ended LVCMOS/LVTTL input
  • Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
  • VCO range: 560MHz – 680MHz
  • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.41ps (typical)
  • Full 2.5V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS 1 1 Phase Detector VCO 625MHz (w/25MHz Reference) M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used OSC F_SEL[1:0] PLL_SEL XTAL_SEL MR REF_CLK XTAL_IN XTAL_OUT Pulldown Pulldown Pulldown Pulldown Pulldown 25MHz ICS844002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin Assignment F_SEL0 VDDA nc PLL_SEL MR VDDO nc VDD VDDO GND nc XTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1

Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 20 V DDO Power Output supply pins. 3, 4 Q0, Q0 Output Differential output pai r. LVDS interface levels.

5 MR Input Pulldown

causing the true outputs Qx to go low and the inverted outputs Qx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.

6 PLL_SEL Input Pulldown

Bypass). LVCMOS/LVTTL interface levels. 8V DDA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10 V DD Power Core supply pins. 14 REF_CLK Input Pulldown Non-inverting differential clock input.

15 XTAL_SEL Input Pulldown

Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. , Q1 Output Differential output pair. LVDS interface levels.

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 3 ICS844002AGI-01 REV. C SEPTEMBER 28, 2007 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 98 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 98 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage 2.5V -0.3 0.7 V IIH Input High Current REF_CLK, MR, FSEL0, FSEL1, PLL_SEL, XTAL_SEL VDD = VIN = 2.625V 150 µA IIL Input Low Current REF_CLK, MR, FSEL0, FSEL1, PLL_SEL, XTAL_SEL VDD = 2.625V, VIN = 0V -5 µA

Table 4. Crystal Characteristics Table 5. AC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 5 ICS844002AGI-01 REV. C SEPTEMBER 28, 2007 Typical Phase Noise at 156.25MHz Ehternet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 6 ICS844002AGI-01 REV. C SEPTEMBER 28, 2007 Parameter Measurement Information 3.3V Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V Output Load AC Test Circuit Output Rise/Fall Time Offset Voltage Setup VDD, VDDO VDDA SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS Qx Qx Qy Qy tsk(o) tPW tPERIOD tPW tPERIOD odc = x 100% Q0, Q1 Q0, Q1 VDD, VDDO VDDA SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND LVDS Clock Outputs 20% 80% 80% 20% tR tF VOD out out LVDSDC Input ➤ VOS/∆ VOS VDD

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 7 ICS844002AGI-01 REV. C SEPTEMBER 28, 2007 Parameter Measurement Information, continued Differential Offset Voltage Setup

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a 0.01µF bypass capacitor should be connected to each V DDA pin. Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 100 out out LVDSDC Input VOD/∆ VOD VDD VDD VDDA 2.5V 10Ω 10µF.01µF .01µF

This section provides information on power dissipation and junction temperature for the ICS844002I-01. Equations and example calculations are also provided. load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection

Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 12 ICS844002AGI-01 REV. C SEPTEMBER 28, 2007

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 13 ICS844002AGI-01 REV. C SEPTEMBER 28, 2007 Revision History Sheet Rev Table Page Description of Change Date C T3B Pin Assignment - correct pin 16 from V DD to nc. Pin Description Table - deleted pin 16 from VDD row. Added Pin 16 row, “nc”. LVCMOS DC Characteristics Table - corrected IIL from -150µA min. to -5µA min. Parameter Measurement Information - corrected Output Rise/Fall Time diagram. Power Considerations - updated calculations. 9/28/07

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