844002

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844002 REVISION B 6/9/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 844002 is a 2 output LVDS Synthesizer optimized to generate Fibre Channel reference clock frequencies. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): The 844002 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The 844002 is packaged in a small 20-pin TSSOP package.

FEATURES

 Two LVDS outputs  Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input  Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz  VCO range: 560MHz - 680MHz  RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.65ps (typical)  Full 3.3V or 2.5V supply modes  0°C to 70°C ambient operating temperature  Available in lead-free (RoHS 6) package Phase Detector VCO 637.5MHz (w/26.5625MHz Reference) M = 24 (fixed) F_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 OSC BLOCK DIAGRAM Inputs Output Frequency (MHz) Input Frequency (MHz) F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Divider Value 26.5625 0 0 24 3 8 212.5 (default) 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 0 24 3 8 187.5 (default) FREQUENCY SELECT FUNCTION TABLE F_SEL[1:0] nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR nQ0 nQ1 Pulldown Pulldown 26.5625MHz Pulldown Pulldown Pulldown 844002 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View PIN ASSIGNMENT

844002 DATA SHEET

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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 3, 4 Q0, nQ0 Ouput Differential output pair. LVDS interface levels.

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abled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 14 REF_CLK Input Pulldown LVCMOS/LVTTL reference clock input. source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. 18, 19 nQ1, Q1 Output Differential output pair. LVDS interface levels. Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, I O Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θ JA 73.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V DD = 3.3V 2 V DD + 0.3 V V DD = 2.5V 1.7 V DD + 0.3 V V IL Input Low Voltage V DD = 3.3V -0.3 0.8 V V DD = 2.5V -0.3 0.7 V I IH Input High Current REF_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, V DD = V IN = 3.465 or 2.5V 150 µA I IL Input Low Current REF_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, V DD = 3.465V or 2.5V, V IN = 0V -150 µA TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO = 3.3V±5%, TA = 0°C TO 70°C TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, V DD = V DDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDA Analog Supply Voltage V DD – 0.12 3.3 V DD V V DDO Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current 105 mA I DDA Analog Supply Current 12 mA I DDO Output Supply Current 120 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 2.375 2.5 2.625 V V DDA Analog Supply Voltage V DD – 0.10 2.5 V DD V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 95 mA I DDA Analog Supply Current 10 mA I DDO Output Supply Current 90 mA

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TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal.

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TABLE 5A. AC CHARACTERISTICS, V DD = V DDO = 3.3V±5%, TA = 0°C TO 70°C TABLE 5B. AC CHARACTERISTICS, V DD = V DDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 15 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 212.5MHz, (637kHz - 10MHz) 0.65 ps 159.375MHz, (637kHz - 10MHz) 0.61 ps 106.25MHz, (637kHz -10MHz) 0.74 ps 53.125MHz, (637kHz - 10MHz) 0.64 ps 187.5MHz, (637kHz - 10MHz) 0.80 ps t R / t F Output Rise/Fall Time 20% to 80% 250 500 ps odc Output Duty Cycle F_SEL[1:0] ≠ ÷3 48 52 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 15 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 212.5MHz, (637kHz - 10MHz) 0.65 ps 159.375MHz, (637kHz - 10MHz) 0.61 ps 106.25MHz, (637kHz -10MHz) 0.74 ps 53.125MHz, (637kHz - 10MHz) 0.64 ps 187.5MHz, (637kHz - 10MHz) 0.80 ps t R / t F Output Rise/Fall Time 20% to 80% 250 500 ps odc Output Duty Cycle F_SEL[1:0] ≠ ÷3 48 52 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

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TYPICAL PHASE NOISE AT 106.25MHZ 106.25MHz RMS Phase Jitter (Random) 637khz to 10MHz = 0.74ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 212.5MHZ -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 212.5MHz RMS Phase Jitter (Random) 637khz to 10MHz = 0.65ps (typical) OFFSET FREQUENCY (HZ) 100 1k 10k 100k 1M 10M 100M dBc Hz NOISE POWER Fibre Channel Jitter Filter Raw Phase Noise Data Phase Noise Result by adding Fibre Channel Filter to raw data Fibre Channel Jitter Filter Raw Phase Noise Data Phase Noise Result by adding Fibre Channel Filter to raw data

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PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUPDIFFERENTIAL OUTPUT VOLTAGE SETUP

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

8 REVISION B 6/9/15

APPLICATION INFORMATION

The 844002 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below FIGURE 2. CRYSTAL INPUT INTERFACE crystal and were chosen to minimize the ppm error. FIGURE 1. POWER SUPPLY FILTERING

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protection, a 1kΩ resistor can be tied from the REF_CLK to ground. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

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3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 Ω differential transmission line environment, LVDS drivers require a matched load termination of 100 Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.FIGURE 4. TYPICAL LVDS DRIVER TERMINATION 2.5V or 3.3V VDD

100 Ohm Differential Transmission Line

LVDS_Driv er

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This section provides information on power dissipation and junction temperature for the 844002. Equations and example calculations are also provided. The total power dissipation for the 844002 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX ) = 3.465V * (105mA + 12mA) = 405.4mW
• Power (outputs) MAX = V DDO_MAX * I DDO_MAX = 3.465V * 120mA = 415.8mW Total Power _MAX = 405.4mW + 415.8mW = 821.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature q JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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TABLE 7. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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TABLE 8. PACKAGE DIMENSIONS

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TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

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Rev Table Page Description of Change Date A 6 Added Phase Noise Plots. 7/24/06 A 11 Power Consideraitons - corrected sentence after the Tj calculation. 1/19/07 A T1 Pin Assignment - corrected Pin 16 from V DD to nc. Pin Description Table - deleted number 16 from VDD row and added row Pin 16 as a “nc”. 9/28/07 B T3A, T3B T5A, T5B Power Supply DC Characteristics Tables - changed VDDA max. from 3.465V to V DD AC Characteristics Tables - corrected NOTE 1. Corrected Output Rise/Fall Time Diagram. Updated Power Supply Filtering Technqiue paragraph text. Corrected Crystal Input Interface Diagram from 33/27p to 18/18p. 7/2/08 Updated data sheet format. 6/9/15

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