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Technical content
Features
- Two differential LVDS outputs
- Selectable crystal oscillator interface or single-ended LVCMOS/LVTTL input
- Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
- VCO range: 560MHz – 680MHz
- RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.41ps (typical)
- Full 3.3V and 2.5V supply modes
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package Phase Detector VCO 625MHz (w/25MHz Reference) M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used OSC F_SEL[1:0] PLL_SEL XTAL_SEL MR REF_CLK XTAL_IN XTAL_OUT Pulldown Pulldown Pulldown Pulldown Pulldown 25MHz 844002-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin Assignment F_SEL0 VDDA nc PLL_SEL MR V DDO nc VDD VDDO GND nc XTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1
Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 20 V DDO Power Output supply pins. 3, 4 Q0, Q0 Output Differential output pai r. LVDS interface levels.
5 MR Input Pulldown
causing the true outputs Qx to go low and the inverted outputs Qx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
6 PLL_SEL
Bypass). LVCMOS/LVTTL interface levels. 8V DDA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10 V DD Power Core supply pins. 14 REF_CLK Input Pulldown Non-inverting differential clock input.
15 XTAL_SEL Input Pulldown
Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. , Q1 Output Differential output pair. LVDS interface levels.
Rev A 6/9/15 3 FEMTOCLOCKS–CRYSTAL -TO-LVDS FREQUENCY SYNTHESIZER 844002-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 3B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.13 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 105 mA IDDA Analog Supply Current 13 mA IDDO Output Supply Current 110 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.12 2.5 V DD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 98 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 98 mA
Table 4. Crystal Characteristics
Rev A 6/9/15 5 FEMTOCLOCKS–CRYSTAL -TO-LVDS FREQUENCY SYNTHESIZER 844002-01 DATA SHEET Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency FSEL[1:0] = 00 140 170 MHz FSEL[1:0] = 01 112 136 MHz FSEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 5 20 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.41 ps 125MHz, (1.875MHz – 20MHz) 0.44 ps 62.5MHz, (1.875MHz – 20MHz) 0.47 ps t R / tF Output Rise/Fall Time 20% to 80% @ 50MHz 250 550 ps odc Output Duty Cycle 48 52 % Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency FSEL[1:0] = 00 140 170 MHz FSEL[1:0] = 01 112 136 MHz FSEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 5 20 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.41 ps 125MHz, (1.875MHz – 20MHz) 0.44 ps 62.5MHz, (1.875MHz – 20MHz) 0.47 ps t R / tF Output Rise/Fall Time 20% to 80% @ 50MHz 250 550 ps odc Output Duty Cycle 48 52 %
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 6 Rev A 6/9/15 844002-01 DATA SHEET Typical Phase Noise at 156.25MHz Ehternet Filter Phase Noise Result by adding a Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)
Rev A 6/9/15 7 FEMTOCLOCKS–CRYSTAL -TO-LVDS FREQUENCY SYNTHESIZER 844002-01 DATA SHEET Parameter Measurement Information 3.3V Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V Output Load AC Test Circuit Output Rise/Fall Time Offset Voltage Setup Parameter Measurement Information, continued VDD, VDDO VDDA3.3V ±5% Qx Qx Qy Qy Q0, Q1 Q0, Q1 VDD, VDDO VDDA SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND 20% 80% 80% 20% tR tF VOD Clock Outputs
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 8 Rev A 6/9/15 844002-01 DATA SHEET Differential Offset Voltage Setup
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 844002-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each V DDA pin. Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. VDD VDDA 3.3V or 2.5V 10Ω 10µF.01µF .01µF
recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination
This section provides information on power dissipation and junction temperature for the 844002-01. Equations and example calculations are also provided. The total power dissipation for the ICS44002-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for HiPerClockS devices is 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. board (single layer or multi-layer). Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP Table 8. Package Dimensions
Rev A 6/9/15 13 FEMTOCLOCKS–CRYSTAL -TO-LVDS FREQUENCY SYNTHESIZER 844002-01 DATA SHEET
Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCKS–CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 14 Rev A 6/9/15 844002-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date AT 1 Pin Assignment - correct pin 16 from VDD to nc. Pin Description Table - deleted pin 16 from VDD row. Added Pin 16 row, “nc”. Parameter Measurement Information - corrected Output Rise/Fall Time diagram. 9/28/07 Updated data sheet format. 6/9/15
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