ICS843N571I IDT | Alldatasheet

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Technical content

Features

  • Fourth generation FemtoClock® Next Generation (NG) technology
  • Seven single-ended LVCMOS outputs, 30Ω output impedance
  • Three LVPECL output pairs One differential LVPECL (QA, nQA) output pair: 156.25MHz Two selectable differential LVPECL output pairs (QB, nQB and QC, nQC): 100MHz and 125MHz
  • One single-ended LVCMOS (QD0) 33.33MHz CPU clock
  • Selectable external crystal or single-ended input source
  • Crystal oscillator interface designed for 25MHz, parallel resonant crystal
  • FemtoClock NG frequency multiplier provides low jitter, high frequency output
  • FemtoClock NG VCO frequency: 2.5GHz
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz – 20MHz): 0.283ps (typical)
  • Power supply noise rejection PSNR: -80dB
  • 3.3V supply voltage
  • -40C to 85C ambient operating temperature
  • Available in lead-free (RoHS 6) packages ICS843N571I 40-Lead VFQFN 6mm x 6mm x 0.925mm package body K Package Top View Pin Assignment

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 2 ©2011 Integrated Device Technology, Inc. Block Diagram ÷16 ÷75 ÷25÷100 XTAL_IN 25MHz OSC PF CP ÷20 REFCLK REFSEL QREF 0 QREF 1 QREF 2 QREF 3 QREF 4 QREF 5 QA nQA QB nQB QC nQC FORCE _LOW FREQSEL QD0 3 -State Decoder FemtoClock NG VCO 25MHz Pulldown Pullup Pulldown Pullup/Pulldown XTAL_OUT

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 3 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 10, 34 V EE Power Negative supply pins. Output Single-ended outputs. 3.3V LVCMOS/LVTTL reference levels. 8 REFCLK Input Pulldown Single-ended LVCMOS/LVTTL reference clock input. REFCLK. See Table 3A. LVCMOS/LVTTL interface levels. 17, 18 QA, nQA Output Differential output pair. LVPECL interface levels. 19, 20 QB, nQB Output Differential output pair. LVPECL interface levels. 21, 22 QC, nQC Output Differential output pair. LVPECL interface levels. 23 QD0 Output Single-ended output. 3.3V LVCMOS/LVTTL reference levels.

27 FREQSEL Input Pullup/

Pulldown Frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. 37 FORCE_LOW Input Pulldown Forces the QD0 output into a low state. See Table 3C. LVCMOS/LVTTL interface levels.

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 4 ©2011 Integrated Device Technology, Inc. Function Tables Table 3A. REFSEL Function Table Table 3B. FREQSEL Function Table Table 3C. FORCE_LOW Function Table Inputs Input Source REFSEL 0R E F C L K 1 (default) XTAL_IN, XTAL_OUT Inputs Output Frequency (MHz) FREQSEL QB, nQB QC, nQC 0 125 125 1 100 100 Float (default) 125 100 Inputs Output Frequency (MHz) FORCE_LOW QD0 0 (default) 33.33 1D i s a b l e d

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 5 ©2011 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 0.3V, VEE = 0V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO (LVCMOS) -0.5V to V CC + 0.5V Outputs, IO (LVPECL) Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 37.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.0 3.3 3.6 V IEE Power Supply Current No Load 250 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage REFSEL, FORCE_LOW 2 V CC + 0.3 V FREQSEL V CC - 0.4 VIL Input Low Voltage REFSEL, FORCE_LOW -0.3 0.8 V FREQSEL 0.4 V VIM Input Medium Voltage FREQSEL V CC/2 - 0.1 V CC/2 + 0.1 V IIH Input High Current REFCLK, FREQSEL, FORCE_LOW VCC = VIN = 3.6V 150 µA REFSEL V CC = VIN = 3.6V 5 µA IIL Input Low Current REFCLK, FORCE_LOW V CC = 3.6V, VIN = 0V -5 µA REFSEL, FREQSEL V CC = 3.6V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 V CC = 3.3V ± 0.3V 2.3 V VOL Output Low Voltage; NOTE 1 V CC = 3.3V ± 0.3V 0.8 V

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 6 ©2011 Integrated Device Technology, Inc. NOTE 1: Outputs teerminated with 50Ω to VCC – 2V. Table 5. Crystal Characteristics NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 7 ©2011 Integrated Device Technology, Inc. Table 6B. AC Characteristics for Single Side Band Power Levels (LVPECL Outputs), VCC = 3.3V ± 0.3V, VEE = 0V, TA = -25°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units ΦN(1k) Single-side band phase noise, 1kHz from Carrier 156.25MHz, 33.33MHz Output disabled -120 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -132 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -135 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -140 dBc/Hz Φ N(10M) Single-side band phase noise, 10MHz from Carrier -156 dBc/Hz ΦN(20M) Single-side band phase noise, 20MHz from Carrier -157 dBc/Hz ΦN(1k) Single-side band phase noise, 1kHz from Carrier 125MHz, 33.33MHz Output disabled -121 dBc/Hz Φ N(10k) Single-side band phase noise, 10kHz from Carrier -133 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -137 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -143 dBc/Hz Φ N(10M) Single-side band phase noise, 10MHz from Carrier -153 dBc/Hz ΦN(20M) Single-side band phase noise, 20MHz from Carrier -153 dBc/Hz ΦN(1k) Single-side band phase noise, 1kHz from Carrier 100MHz, 33.33MHz Output disabled -123 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -135 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -139 dBc/Hz Φ N(1M) Single-side band phase noise, 1MHz from Carrier -145 dBc/Hz ΦN(10M) Single-side band phase noise, 10MHz from Carrier -154 dBc/Hz ΦN(20M) Single-side band phase noise, 20MHz from Carrier -154 dBc/Hz

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 8 ©2011 Integrated Device Technology, Inc. Table 6C. LVCMOS AC Characteristics, VCC = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCC/2. Table 6D. AC Characteristics for Single Side Band Power Levels (LVCMOS Outputs), VCC = 3.3V ± 0.3V, VEE = 0V, TA = -25°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditions Minimum Typical Maximum Units fIN Input Frequency 25 MHz fOUT Output Frequency 25 33.33 MHz tjit(θ) RMS Phase Jitter (Random) NOTE 1 33.33MHz fOUT, 25MHz crystal Integration Range: 12kHz – 5MHz 0.266 ps 25MHz fOUT, 25MHz crystal Integration Range: 12kHz – 5MHz 0.212 ps tsk(o) Output Skew; NOTE 2, 3 QREF[ 0:5] Measured on the Rising Edge 50 ps PSNR Power Supply Noise Reduction Pin 40, CC) From DC to 6.25MHz -80 dB tR / tF Output Rise/Fall Time 20% to 80% 200 600 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units ΦN(1k) Single-side band phase noise, 1kHz from Carrier 33.33MHz -134 dBc/Hz ΦN(10k) Single-side band phase noise, 10kHz from Carrier -144 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -149 dBc/Hz Φ N(1M) Single-side band phase noise, 1MHz from Carrier -153 dBc/Hz ΦN(5M) Single-side band phase noise, 5MHz from Carrier -159 dBc/Hz ΦN(1k) Single-side band phase noise, 1kHz from Carrier 25MHz -137 dBc/Hz Φ N(10k) Single-side band phase noise, 10kHz from Carrier -152 dBc/Hz ΦN(100k) Single-side band phase noise, 100kHz from Carrier -158 dBc/Hz ΦN(1M) Single-side band phase noise, 1MHz from Carrier -160 dBc/Hz Φ N(5M) Single-side band phase noise, 5MHz from Carrier -160 dBc/Hz

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 9 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 25MHz (LVCMOS Output) Typical Phase Noise at 33.33MHz (LVCMOS Output) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 10 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 100MHz (LVPECL Output) Typical Phase Noise at 125MHz (LVPECL Output) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 11 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 156.25MHz (LVPECL Output) Noise Power dBc Hz Offset Frequency (Hz)

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 12 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information LVPECL Output Load AC Test Circuit Phase Jitter LVPECL Output Skew LVCMOS Output Load AC Test Circuit LVCMOS Output Skew LVCMOS Output Rise/Fall Time SCOPE Qx nQx VEE VCC -1.3V ± 0.3V Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power nQx Qx nQy Qy tsk(o) SCOPE Qx VEE VCC 1.65V ± 0.15V -1.65V ± 0.15V tsk(o) VCC VCC QREFx QREFy 20% 80% 80% 20% tR tF QD0, QREF[0:5]

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 13 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued LVPECL Output Rise/Fall Time LVPECL Output Duty Cycle/Pulse Width/Period LVCMOS Output Duty Cycle/Pulse Width/Period 20% 80% 80% 20% tR tF VSWING nQ[A:C] Q[A:C] tPW tPERIOD tPW tPERIOD odc = x 100% nQ[A:C] Q[A:C] tPERIOD tPW tPERIOD odc = VCC tPW x 100% QD0, QREF[0:5]

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 15 ©2011 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 16 ©2011 Integrated Device Technology, Inc. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination Recommendations for Unused Input and Output Pins Inputs: REFCLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REFCLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. LVPECL Outputs: All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 17 ©2011 Integrated Device Technology, Inc. Figure 4 shows an example of ICS843N571I application schematic. 15pF and C2 = 15pF are recommended for frequency accuracy. crystal load capacitors are required for proper operation. can be on the opposite side of the PCB. the general area of all devices. Figure 4. ICS843S571I Application Schematic

25 M Hz

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 18 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843N571I. Equations and example calculations are also provided. The total power dissipation for the ICS843N571I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 37.7°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 40 Lead VFQFN Forced Convection

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 19 ©2011 Integrated Device Technology, Inc.

  1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 5. Figure 5. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 20 ©2011 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 40 Lead VFQFN

ICS843N571AKI REVISION A SEPTEMBER 29, 2011 21 ©2011 Integrated Device Technology, Inc. Table 9. Package Dimensions package dimensions are in Table 9.

  1. Type A: Chamfer on the paddle (near pin 1)
  2. Type C: Mouse bite on the paddle (near pin 1)

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER ICS843N571AKI REVISION A SEPTEMBER 29, 2011 22 ©2011 Integrated Device Technology, Inc.

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS843N571I Data Sheet FEMTOCLOCK NG® CLOCK SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

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