843N252-45 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Fourth generation FemtoClock® Next Generation (NG) technology
  • One differential 3.3V LVPECL output and one LVCMOS/LVTTL output
  • Crystal oscillator interface designed for a 25MHz parallel resonant crystal
  • A 25MHz crystal generates output frequencies of: 156.25MHz and 125MHz
  • VCO frequency: 625MHz
  • RMS Phase Jitter @ 156.25MHz, (12kHz – 20MHz) using a 25MHz crystal: 0.33ps (typical)
  • RMS Phase Jitter @ 125MHz, (12kHz – 20MHz) using a 25MHz crystal: 0.39ps (typical)
  • Power supply noise rejection PSNR: -60dB (typical)
  • Full 3.3V supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 843N252-45 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package OSC PFD LPF Feedback Divider ÷25 ÷525MHz QA QB nQB CLK_ENA XTAL_IN XTAL_OUT CLK_ENB Pullup Pullup FemtoClock®NG VCO 625MHz 9VCC VCCA nc nc VCCOA QA VEE CLK_ENA CLK_ENB VEE QB nQB VCC XTAL_IN XTAL_OUT VEE 843N252-45 Data Sheet FemtoClock ® NG Crystal-to-3.3V LVPECL Frequency Synthesizer

Table 1. Pin Descriptions Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK_ENA Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3A. 2, 9, 15 V EE Power Negative supply pins. 3 QA Output Single-ended clock output. LVCMOS/LVTTL interface levels. 4V CCOA Power Output supply pin for QA output. 7V CCA Power Analog supply pin. 8, 12 V CC Power Power supply pin. XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. 13, 14 nQB, QB Output Differential ou tput pair. LVPECL interface levels. 16 CLK_ENB Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3B.

0 High-Impedance

1 Active

1 Active Active

3©2016 Integrated Device Technology, Inc Revision A April 20, 2016 843N252-45 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCOA = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCOA = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to VCCOA/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuos Current Surge Current -0.5V to VCCOA + 0.5V 50mA 100mA Package Thermal Impedance, JA 94.8C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.14 3.3 V CC V VCCOA Power Supply Voltage 3.135 3.3 3.465 V ICCA Analog Supply Current 14 mA IEE Power Supply Current No Load 124 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_ENA, CLK_ENB VCC = VIN = 3.465V 5 µA IIL Input Low Current CLK_ENA, CLK_ENB VCC = 3.465V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 V CCOA = 3.3V ± 5% 2.3 V VOL Output Low Voltage; NOTE 1 V CCOA = 3.3V ± 5% 0.5 V

NOTE 1: Output termination with 50 to VCC – 2V. Table 5. Crystal Characteristics Table 6. AC Characteristics, VCC = VCCOA = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C has been reached under these conditions. NOTE: Using a 25MHz, 12pF quartz crystal. NOTE 1: Please refer to the Phase Noise plots.

5©2016 Integrated Device Technology, Inc Revision A April 20, 2016 843N252-45 Data Sheet Typical Phase Noise at 125MHz Typical Phase Noise at 156.25MHz 125MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.39ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.33ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

6©2016 Integrated Device Technology, Inc Revision A April 20, 2016 843N252-45 Data Sheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter LVCMOS Output Duty Cycle/Pulse Width/Period 3.3V LVCMOS Output Load AC Test Circuit LVPECL Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time VCC -1.3V± 0.165V VCCA tPERIOD tPW tPERIOD odc = x 100% tPW QA SCOPE Qx GND 1.65V±5% -1.65V±5% VCCOA VCCA VCC, 1.65V±5% nQB QB 20% 80% 80% 20% tR tF VSWING nQB QA, QB

Figure 3. 843N252-45 Schematic Example

10©2016 Integrated Device Technology, Inc Revision A April 20, 2016 843N252-45 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 843N252-45. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843N252-45 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Core and LVPECL Output Power Dissipation  Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 124mA = 429.66mW  Power (LVPECL) = 33.75mW/Loaded Output pair LVCMOS Output Power Dissipation  Output Impedance R OUT Power Dissipation due to Loading 50 to VCCOA/2 Output Current IOUT = VCCOA_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.65mA  Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.65mA)2 = 10.65mW per output  Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VCCOA)2 = 7pF * 125MHz * (3.465V)2 = 10.51mW Total Power Dissipation  Total Power = Power (core) + Power (LVPECL) + Power (ROUT) + Power (125MHz) = 429.66mW + 33.75mW + 10.65mW + 10.51mW = 484.57mW

wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 94.8°C/W per Table 7 below. Table 7. Thermal Resistance JA for 16 Lead TSSOP Forced Convection

Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP

14©2016 Integrated Device Technology, Inc Revision A April 20, 2016 843N252-45 Data Sheet

Ordering Information

Table 10. Ordering Information

15©2016 Integrated Device Technology, Inc Revision A April 20, 2016 843N252-45 Data Sheet Revision History Sheet Rev Table Page Description of Change Date A Removed ICS from the part number where needed. Ordering information - Removed quantity from tape and reel. Deleted LF note below table. Updated data sheet header and footer. 4/20/16

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