843N001I

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Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator 843N001I DATASHEET 873991-147 REVISION B 8/25/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 873991-147 is a low voltage, low skew, 3.3V LVPECL or ECL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 873991-147 has two selectable clock inputs. The CLK, nCLK pair can accept LVPECL, LVDS, LVHSTL, SSTL and HCSL input levels and, the REF_CLK pin can accept a LVCMOS or LVTTL input levels. This device has a fully integrated PLL along with frequency confi gurable outputs. An external feedback input and output regenerates clocks with “zero delay”. The four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of differ- ent bank frequency ratios and output-to-input frequency ratios. The output frequency range is 25MHz to 480MHz and the input frequency range is 6.25MHz to 120MHz. The PLL_EN input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. The 873991-147 also has a SYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other. Example Applications: 1. Line Card Multiplier: Multiply 19.44MHz from a back-plane to 77.76MHz on the line card ASIC and Serdes. 2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies from a reference clock to multiple processing units on an embedded system.

FEATURES

• Fourteen differential 3.3V LVPECL/ECL outputs
• Selectable differential or REF_CLK inputs
• CLK, nCLK can accept the following input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• REF_CLK accepts the following input levels: LVCMOS, LVTTL
• Input clock frequency range: 6.25MHz to 120MHz
• Maximum output frequency: 480MHz
• VCO range: 200MHz to 960MHz
• Output skew: 250ps (maximum), outputs at the same frequency
• Cycle-to-cycle jitter: 55ps (maximum)
• LVPECL mode operating voltage supply range: V CC = 3.135V to 3.465V, V EE = 0V
• ECL mode operating voltage supply range: V CC = 0V, V EE = -3.465V to -3.135V
• 0°C to 50°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Use replacement part 873996AYLF PIN ASSIGNMENT

2 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

VCO_SEL PLL_EN REF_SEL REF_CLK CLK nCLK EXT_FB nEXT_FB MR FSEL_0:3 FSEL_FB0:2 SYNC_SEL QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 QC0 nQC0 QC1 nQC1 QC2 nQC2 QD0 nQD0 QD1 nQD1 QFB nQFB BLOCK DIAGRAM Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pullup/Pulldown Pulldown Pullup/Pulldown Pulldown

3 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 1. PIN DESCRIPTIONS

2 MR Input Pulldown

are enabled. LVCMOS/LVTTL interface levels. is in bypass mode. LVCMOS/LVTTL interface levels.

4 REF_SEL Input Pulldown

REF_CLK. LVCMOS/LVTTL interface levels. Input Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels. 8 REF_CLK Input Pulldown Reference clock input. LVCMOS/LVTTL interface levels. 9 CLK Input Pulldown Non-inverting differential clock input. /2 default when left fl oating. 12 EXT_FB Input Pulldown Non-inverting external feedback input. /2 default when left fl oating. QFB Output Differential feedback output pair. LVPECL Interface levels. 18, 19 nQD0, QD0 Output Differential output pair. LVPECL interface levels. 20, 21 nQD1, QD1 Output Differential output pair. LVPECL interface levels. 23, 24 nQC0, QC0 Output Differential output pair. LVPECL interface levels. 25, 26 nQC1, QC1 Output Differential output pair. LVPECL interface levels. Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 28, 29 nQC2, QC2 Output Differential output pair. LVPECL interface levels. 31, 32 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 34, 35 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 37, 38 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 40, 41 nQB3, QB3 Output Differential output pair. LVPECL interface levels. 43, 44 nQA0, QA0 Output Differential output pair. LVPECL interface levels. 45, 46 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 47, 48 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 49, 50 nQA3, QA3 Output Differential output pair. LVPECL interface levels.

51 SYNC_SEL Input Pulldown

52 VCO_SEL Input Pulldown Selects VCO range. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

4 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 2. PIN CHARACTERISTICS

5 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

FIGURE 1. TIMING DIAGRAMS

6 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 3.3V ± 5%, V EE = 0V, TA = 0°C TO 50°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC - 0.15 3.3 V CC V V CCO Output Supply Voltage 3.135 3.3 3.465 V I CC Power Supply Current 150 mA I CCA Analog Supply Current 15 mA I CCO Output Supply Current 95 mA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 55.5°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect product reliability. TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V CC = V CCO = 3.3V ± 5%, V EE = 0V, TA = 0°C TO 50°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage PLL_EN, VCO_SEL, REF_SEL, SYNC_SEL, FSEL_FB0:FSEL_FB2, FSEL0:FSEL3, MR CC + 0.3 V REF_CLK 2 V CC + 0.3 V V IL Input Low Voltage PLL_EN, VCO_SEL, REF_SEL, SYNC_SEL, FSEL_FB0:FSEL_FB2, FSEL0:FSEL3, MR -0.3 0.8 V REF_CLK -0.3 1.3 V I IH Input High Current V CC = V IN = 3.465V 150 µA I IL Input Low Current V IN = 0V, V CC = 3.465V -5 µA

7 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, V NOTE: These parameters are guaranteed by design, but are not tested in production. should not be less than -0.3V.

8 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 6. AC CHARACTERISTICS, V device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency. when the PLL is locked and the input reference frequency is stable. NOTE 3: Static phase offset is specifi ed for an input frequency of 50MHz with feedback in ÷8. NOTE 4: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 7: This value is based on the VCO frequency = 960MHz, output divider = 2. NOTE 8: This value is based on the VCO frequency = 480MHz, output divider = 2. NOTE 9: When VCO_SEL = 0, the PLL will be unstable with feedback confi gurations of ÷2, ÷4, ÷32 and some ÷6. When VCO_SEL = 1, the PLL will be unstable with a feedback confi guration of ÷2.

9 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

PARAMETER MEASUREMENT INFORMATION OUTPUT RISE/FALL TIME OUTPUT LOAD AC TEST CIRCUIT -1.3V ± -0.165V V CC V CCO HALF-CYCLE JITTER OUTPUT SKEW MULTIPLE FREQUENCY SKEW DIFFERENTIAL INPUT LEVELS tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

V CMR Cross PointsV PP V CC V EE CLK nCLK OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tsk(ω) nQxx Qxx nQyy Qyy nQFB, nQAx:nQDx QFB, QAx:QDx tjit(hcyc) = |hcyc n – hcyc n+1| QFB, QAx:QDx nQFB, nQAx:nQDx STATIC PHASE OFFSET QFB, QAx:QDx nQFB, nQAx:nQDx V CCA

10 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT FIGURE 2. POWER SUPPLY FILTERING

11 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

FIGURE 4C. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4B. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4D. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. FIGURE 4A. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 4A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V FIGURE 4E. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER FIGURE 4F. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER

12 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS INPUTS: CLK/nCLK INPUTS For applications not requiring the use of a differential input, both the CLK and nCLK pins can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS C ONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

13 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

only two termination examples are shown in this schematic. FIGURE 6. 873991-147 SCHMATIC LAYOUT

14 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 7. THERMAL RESISTANCE θJA FOR 52-PIN LQFP FORCED CONVECTION This section provides information on power dissipation and junction temperature for the 873991-147. Equations and example calculations are also provided. = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = V CC_MAX * (I CC_MAX + I CCA_MAX + I CCO_MAX ) = 3.465V * (150mA + 15mA + 95mA) = 900.9mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 14 * 30mW = 420mW Total Power _MAX (3.465V, with all outputs switching) = 900.9mW + 420mW = 1.3209W 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = J unction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 55.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 50°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (multi-layer). θJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 55.5°C/W 50.1°C/W 47.0°C/W

15 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

1. Calculations and Equations.

pose of this section is to derive the power dissipated into the load.

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX ) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R L ] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX ))/R L ] * (VCCO_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/R L ] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX ))/R L ] * (VCCO_MAX – VOL_MAX) = [(2V Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

16 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 8. θ

17 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

TABLE 9. PACKAGE DIMENSIONS

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TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

19 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL

Rev Table Page Description of Change Date AT 6 8 AC Characteristics Table - corrected symbol for Half Cycle Jitter. Power Considerations - corrected I EE_MAX from 150mA to 165mA and recalulated equations. Deleted the word Preliminary from inside page headers. 11/18/08 B T4A T4C T4D Changed from 0°C to 70°C to 0°C to 50°C throughout the datasheet. Changed PCLK/nPCLK to CLK/nCLK throughout the datasheet. Power Supply DC Characteristics Table - changed V CCA from 3.135V min to V CC 0.15V and 3.465V max. to V CC. Added Differential DC Characteristics Table for CLK/nCLK and EXT_FB/nEXT_ FB inputs. Updated LVPECL DC Characteristics Table for LVPECL outputs. AC Characteristics Table - corrected Half-Cycle Jitter symbol from tjit(hper) to tjit(hcyc). Updated Differential Clock Input Interface section. Added Schematic Layout. Power Considerations - corrected I EE _MAX from 165mA to 260mA, updated Ther- mal Resistance values in Table 7, and recalculated equations. Air Flow Table - updated the values. 3/31/09 B Product Discontinuation Notice - Last time buy expires August 14, 2016. PDN CQ-15-04 8/25/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.