ICS843801I-24 RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • One differential 3.3V, 2.5V LVPECL output
  • Crystal oscillator interface, 18pF parallel resonant crystal (21.5625MHz - 25.3125MHz)
  • Output frequency range: 172.5MHz - 202.5MHz, and 345MHz - 405MHz
  • VCO range: 690MHz – 810MHz
  • RMS phase jitter at 400MHz, using a 25MHz crystal (12kHz – 20MHz): 0.88ps (typical), @ 3.3V
  • Full 3.3V or 2.5V operating supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Common Configuration Table Inputs Output Frequency (MHz)Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N 25 0 32 2 16 400 25 1 (default) 32 4 8 200 VCCA XTAL_OUT XTAL_IN VEE VCC Q nQ FREQ_SEL Pin Assignment ICS843801I-24

8 Lead TSSOP

4.40mm x 3.0mm x 0.925 package body G Package Top View OSC Phase Detector VCO 690MHz - 810MHz M = ÷32 (fixed) FREQ_SEL N 0 ÷2 1 (default) ÷4 Q nQ PullupFREQ_SEL XTAL_IN XTAL_OUT Block Diagram

ICS843801AGI-24 REVISION A AUGUST 10, 2011 2 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 4V EE Power Negative supply pin. 5 FREQ_SEL Input Pullup Frequency select pi n, LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differ ential output pair. LVPECL interface levels. 8V CC Power Core supply pin.

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 3 ©2011 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.09 3.3 V CC V ICC Power Supply Current 66 mA ICCA Analog Supply Current 9m A IEE Power Supply Current 72 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage V CC – 0.09 2.5 V CC V ICC Power Supply Current 60 mA ICCA Analog Supply Current 9m A IEE Power Supply Current 72 mA

ICS843801AGI-24 REVISION A AUGUST 10, 2011 4 ©2011 Integrated Device Technology, Inc. NOTE 1: Outputs termination with 50Ω to VCC – 2V. NOTE 1: Outputs termination with 50Ω to VCC – 2V. Table 4. Crystal Characteristics

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 5 ©2011 Integrated Device Technology, Inc. Table 5A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. Table 5B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency 172.5 202.5 MHz 345 405 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 200MHz, Integration Range: 12kHz – 20MHz 0.87 1.02 ps 400MHz, Integration Range: 12kHz – 20MHz 0.88 0.98 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 13 ps tjit(per) RMS Period Jitter 0.18 2.1 ps tL PLL Lock Time 10 ms tR / tF Output Rise/Fall Time 20% to 80% 200 500 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 172.5 202.5 MHz 345 405 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 200MHz, Integration Range: 12kHz – 20MHz 0.87 1.05 ps 400MHz, Integration Range: 12kHz – 20MHz 0.89 1.06 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 16 ps tjit(per) RMS Period Jitter 0.20 2.6 ps tL PLL Lock Time 10 ms tR / tF Output Rise/Fall Time 20% to 80% 200 500 ps odc Output Duty Cycle 48 52 %

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 6 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 200MHz, (3.3V) Noise Power dBc Hz 200MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.87ps (typical) Offset Frequency (Hz)

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 7 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 400MHz, (3.3V) Noise Power dBc Hz 400MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.88ps (typical) Offset Frequency (Hz)

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 8 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Period Jitter 2.5V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx LVPECL VEE VCC VCCA -1.3V ± 0.165V ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram SCOPE Qx nQx LVPECL VEE VCC VCCA -0.5V ± 0.125V Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power nQ tPW tPERIOD tPW tPERIOD odc = x 100% Q

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 9 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Rise/Fall Time PLL Lock Time 20% 80% 80% 20% tR tF VSWING nQ Q

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 11 ©2011 Integrated Device Technology, Inc. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS843801AGI-24 REVISION A AUGUST 10, 2011 14 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843801I-24. Equations and example calculations are also provided. The total power dissipation for the ICS843801I-24 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Table 6. Thermal Resitance θJA for 8 Lead TSSOP, Forced Convection

ICS843801AGI-24 REVISION A AUGUST 10, 2011 15 ©2011 Integrated Device Technology, Inc.

  1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 5. Figure 5. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

ICS843801AGI-24 REVISION A AUGUST 10, 2011 16 ©2011 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ICS843801AGI-24 REVISION A AUGUST 10, 2011 17 ©2011 Integrated Device Technology, Inc.

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS843801I-24 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

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