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Document overview
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Technical content
Features
- Designed for use in SAS, SAS-2 systems
- Up, down and center Spread Spectrum Clocking (SSC)
- One differential 3.3V or 2.5V LVPECL output pair
- Output frequency: 75MHz
- RMS phase jitter @ 75MHz, (900kHz – 7.5MHz): 0.734ps (typical) @ 3.3V
- 3.3V or 2.5V operating supply modes
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- Functional replacement part: 843002AYLF Block Diagram Pin Assignment 843751 8-Lead SOIC, 150 Mil 3.90mm x 4.90mm x 1.375mm package body M Package Top View OSC FemtoClock™ PLL Q nQ XTAL_IN XTAL_OUT SSC_SEL[1:0] 75MHz25MHz Pulldown
843751 Data Sheet FEMTOCLOCK™ SAS/SATA CLOCK GENERATOR
843751 REVISION B 08.21.15 2 ©2015 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. SSC_SEL[1:0] Function Table XTAL_IN Input Crystal oscillator interface. XTAL _IN is the input, XTAL_OUT is the output. SSC_SEL1 Input Pulldown SSC select pins. See Tabl e 3A. LVCMOS/LVTTL interface levels. 5V CC Power Power supply pin. 6, 7 Q, nQ Output Differential clock outputs. LVPECL interface levels. 8V EE Power Negative supply pin.
843751 REVISION B 08.21.15 3 ©2015 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4C. LVCMOS/LVTTL DC Characteristics,VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 96°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 77 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 75 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.3V 2 V CC + 0.3 V VCC = 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V IIH Input High Current SSC_SEL[0:1] V CC = VIN = 3.465V or 2.5V 150 µA IIL Input Low Current SSC_SEL[0:1] V CC = 3.465V or 2.5V, VIN = 0V -5 µA
843751 REVISION B 08.21.15 4 ©2015 Integrated Device Technology, Inc. NOTE 1: Output termination with 50 to VCC – 2V. NOTE 1: Output termination with 50 to VCC – 2V. Table 5. Crystal Characteristics
843751 REVISION B 08.21.15 5 ©2015 Integrated Device Technology, Inc. Table 6A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to the Phase Noise plot. Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to the Phase Noise plot. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 75 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 75MHz, Integration Range: 900kHz – 7.5MHz 0.734 ps tR / tF Output Rise/Fall Time 20% to 80% 325 575 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 75 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 75MHz, Integration Range: 900kHz – 7.5MHz 0.755 ps tR / tF Output Rise/Fall Time 20% to 80% 325 575 ps odc Output Duty Cycle 48 52 %
843751 REVISION B 08.21.15 6 ©2015 Integrated Device Technology, Inc. Typical Phase Noise at 75MHz at 3.3V 75MHz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.734ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
843751 REVISION B 08.21.15 7 ©2015 Integrated Device Technology, Inc. Typical Phase Noise at 75MHz at 2.5V 75MHz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.755ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
843751 REVISION B 08.21.15 8 ©2015 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC -1.3V ± 0.165V nQ Q SCOPE Qx nQx VEE VCC -0.5V ± 0.125V nQ Q
843751 REVISION B 08.21.15 9 ©2015 Integrated Device Technology, Inc.
Application Information
The 843751 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface
843751 REVISION B 08.21.15 10 ©2015 Integrated Device Technology, Inc. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
843751 REVISION B 08.21.15 11 ©2015 Integrated Device Technology, Inc. Termination for 2.5V LVPECL Outputs Figure 4A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC= 2.5V, the VCC– 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4C. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V LVPECL Driver VCC = 2.5V 2.5V 2.5V 50Ω 50Ω 250Ω 250 Ω 62.5 Ω 62.5 Ω 2.5V LVPECL Driver VCC = 2.5V 2.5V 50Ω 50Ω 50Ω Ω 2.5V LVPECL Driver VCC = 2.5V 2.5V 50Ω 50Ω 50Ω Ω Ω
843751 REVISION B 08.21.15 12 ©2015 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the 843751. Equations and example calculations are also provided. The total power dissipation for the 843751 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 77mA = 266.8mW
- Power (outputs) MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 266.8mW + 30mW = 296.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.297W * 96°C/W = 98.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
843751 REVISION B 08.21.15 13 ©2015 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 5. Figure 5. LVPECL Driver Circuit and Termination
- For logic high, V OUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V
- For logic low, V OUT = VOL_MAX = VCO_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW VOUT VCC VCC - 2V RL 50Ω
843751 REVISION B 08.21.15 14 ©2015 Integrated Device Technology, Inc. Table 8. JA vs. Air Flow Table for a 8 Lead SOIC
843751 REVISION B 08.21.15 15 ©2015 Integrated Device Technology, Inc.
Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
843751 REVISION B 08.21.15 16 ©2015 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date B 1 PDN #CQ-15-04 Product Discontinuance Notice – Last Time buy Expires on August 14, 2016. 08/21/15
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