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Technical content

Features

  • Designed for use in SAS, SAS-2, and SATA systems
  • Center (±0.25%) Spread Spectrum Clocking (SSC)
  • Down (-0.23% or -0.5%) SSC
  • Two differential 3.3V LVPECL output pairs
  • Crystal oscillator interface designed for 25MHz (CL = 18pF) frequency
  • External fundamental crystal frequency ensures high reliability and low aging
  • Selectable output frequencies: 75MHz, 150MHz
  • Output frequency is tunable with external capacitors
  • RMS phase jitter at 150MHz (integrated from 12kHz to 20MHz): 1.07ps (typical)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • Functional replacement part: 843002AYLF Block Diagram Pin Assignment 843442 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View OSC nQ0 XTAL_IN XTAL_OUT 25MHz SSC_SEL[1:0] nPLL_SEL nQ1 FemtoClock™ PLL Clock Output Control Logic Pulldown Pulldown F_SEL Pullup 0 = 75MHz 1 = 150MHz (default) 9SSC_SEL1 nc nc nc SSC_SEL0 XTAL_IN XTAL_OUT VEE F_SEL VEE nPLL_SEL nQ0 nQ1 VCC

843442AG REVISION B 08/21/2015 2 ©2015 Integrated Device Technology, Inc.

843442 Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator

Table 1. Pin Descriptions NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 15 V EE Power Negative supply pins. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. 5, 6, 7 nc Unused No connect. 9V CC Power Power supply pin. 10, 11 Q1, nQ1 Output Differential clo ck outputs. LVPECL interface levels. 12, 13 Q0, nQ0 Output Differential clo ck outputs. LVPECL interface levels. 14 nPLL_SEL Input Pulldown PLL Bypass pin. When LOW, selects PLL. When HIGH, bypasses PLL. LVCMOS/LVTTL interface levels. 16 F_SEL Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.

843442AG REVISION B 08/21/2015 3 ©2015 Integrated Device Technology, Inc. NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Output termination with 50 to VCC – 2V. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 92.4°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 80 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current F_SEL V CC = VIN = 3.465V 5 µA nPLL_SEL, SSC_SEL[0:1] VCC = VIN = 3.465V 150 µA IIL Input Low Current F_SEL V CC = 3.465V, VIN = 0V -150 µA nPLL_SEL, SSC_SEL[0:1] VCC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CC – 1.4 V CC – 0.9 V VOL Output Low Voltage; NOTE 1 V CC – 2.0 V CC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 0.9 V

843442AG REVISION B 08/21/2015 4 ©2015 Integrated Device Technology, Inc. Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE 1: See phase noise plot section.

843442AG REVISION B 08/21/2015 5 ©2015 Integrated Device Technology, Inc. Typical Phase Noise at 75MHz Typical Phase Noise at 150MHz Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)

843442AG REVISION B 08/21/2015 6 ©2015 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Rise/Fall Time RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC -1.3V± 0.165V nQ[0:1] Q[0:1] Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ[0:1] Q[0:1]

843442AG REVISION B 08/21/2015 7 ©2015 Integrated Device Technology, Inc.

Application Information

The 843442 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface

843442AG REVISION B 08/21/2015 8 ©2015 Integrated Device Technology, Inc. Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

843442AG REVISION B 08/21/2015 9 ©2015 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the 843442. Equations and example calculations are also provided. The total power dissipation for the 843442 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW
  • Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 277.2mW + 60mW = 337.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).

Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection

843442AG REVISION B 08/21/2015 10 ©2015 Integrated Device Technology, Inc.

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination

  • For logic high, V OUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V
  • For logic low, V OUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW VOUT VCC VCC - 2V RL 50Ω

843442AG REVISION B 08/21/2015 11 ©2015 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP

843442AG REVISION B 08/21/2015 12 ©2015 Integrated Device Technology, Inc.

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

843442AG REVISION B 08/21/2015 13 ©2015 Integrated Device Technology, Inc. Rev Table Page Description of Change Date B 1 PDN #CQ-15-04 Product Discontinuance Notice – Last Time buy Expires on August 14, 2016. 08/21/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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