ICS843442I IDT | Alldatasheet
Document overview
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Technical content
Features
- Designed for use in SAS, SAS-2, and SATA systems
- Center (±0.25%) Spread Spectrum Clocking (SSC)
- Down (-0.23% or -0.5%) SSC
- Two differential 3.3V LVPECL output pairs
- Crystal oscillator interface designed for 25MHz (CL = 18pF) frequency
- External fundamental crystal frequency ensures high reliability and low aging
- Selectable output frequencies: 75MHz, 150MHz
- Output frequency is tunable with external capacitors
- RMS phase jitter at 150MHz (integrated from 12kHz to 20MHz): 1.07ps (typical)
- 3.3V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package HiPerClockS™ ICS Block Diagram Pin Assignment ICS843442I 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View OSC nQ0 XTAL_IN XTAL_OUT 25MHz SSC_SEL[1:0] nPLL_SEL nQ1 FemtoClock™ PLL Clock Output Control Logic Pulldown Pulldown F_SEL Pullup 0 = 75MHz 1 = 150MHz (default) 9SSC_SEL1 nc nc nc SSC_SEL0 XTAL_IN XTAL_OUT VEE F_SEL VEE nPLL_SEL nQ0 nQ1 VCC
ICS843442AGI REVISION A JUNE 24, 2009 2 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 15 V EE Power Negative supply pins. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. SSC_SEL1 Input Pulldown SSC select pins. See Tabl e 3A. LVCMOS/LVTTL interface levels. 5, 6, 7 nc Unused No connect. 9V CC Power Power supply pin. 10, 11 Q1, nQ1 Output Differential clo ck outputs. LVPECL interface levels. 12, 13 Q0, nQ0 Output Differential clo ck outputs. LVPECL interface levels. 14 nPLL_SEL Input Pulldown PLL Bypass pin. When LOW, selects PLL. When HIGH, bypasses PLL. LVCMOS/LVTTL interface levels. 16 F_SEL Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
ICS843442AGI REVISION A JUNE 24, 2009 3 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Output termination with 50Ω to VCC – 2V. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 92.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 80 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current F_SEL V CC = VIN = 3.465V 5 µA nPLL_SEL, SSC_SEL[0:1] VCC = VIN = 3.465V 150 µA IIL Input Low Current F_SEL V CC = 3.465V, VIN = 0V -150 µA nPLL_SEL, SSC_SEL[0:1] VCC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VOH Output High Voltage; NOTE 1 V CC – 1.4 V CC – 0.9 V VOL Output Low Voltage; NOTE 1 V CC – 2.0 V CC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 0.9 V
ICS843442AGI REVISION A JUNE 24, 2009 4 ©2009 Integrated Device Technology, Inc. Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: See phase noise plot section.
ICS843442AGI REVISION A JUNE 24, 2009 5 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator Typical Phase Noise at 75MHz Typical Phase Noise at 150MHz Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)
ICS843442AGI REVISION A JUNE 24, 2009 6 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Rise/Fall Time RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx LVPECL VEE VCC -1.3V± 0.165V 20% 80% 80% 20% tR tF VSWING nQ[0:1] Q[0:1] Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPW tPERIOD tPW tPERIOD odc = x 100% nQ[0:1] Q[0:1]
ICS843442AGI REVISION A JUNE 24, 2009 8 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V
ICS843442AGI REVISION A JUNE 24, 2009 9 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843442I. Equations and example calculations are also provided. The total power dissipation for the ICS843442I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for HiPerClockS devices is 125°C. a multi-layer board, the appropriate value is 92.4°C/W per Table 6 below. board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
ICS843442AGI REVISION A JUNE 24, 2009 10 ©2009 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
ICS843442AGI REVISION A JUNE 24, 2009 11 ©2009 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 16 Lead TSSOP
ICS843442AGI REVISION A JUNE 24, 2009 12 ©2009 Integrated Device Technology, Inc. ICS843442I Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator
Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.
ICS843442I Data Sheet FEMTOCLOCK™ SAS/SAT A Clock Generator DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.
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