843441 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 18
Technical content
Features
- Designed for use in SAS, SAS-2, and SATA systems
- Center (±0.33%) Spread Spectrum Clocking (SSC)
- Down (-0.30% or -0.60%) SSC
- Better frequency stability than SAW oscillators
- One differential 3.3V LVPECL output
- Crystal oscillator interface designed for 25MHz (CL = 18pF) frequency
- External fundamental crystal frequency ensures high reliability and low aging
- Selectable output frequencies: 75MHz, 100MHz, 150MHz, 300MHz
- Output frequency is tunable with external capacitors
- RMS phase jitter: 1.33ps (typical)
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Industrial temperature available upon request
- Available in lead-free (RoHS 6) package
- 843441-150 Functional replacement part use 8T49N242i Part/Order Number Package Output Frequency (MHz) 843441AG 16 TSSOP 75, 100, 150, 300 843441AM-75 8 SOIC 75 843441AM-100 8 SOIC 100 843441AM-150 8 SOIC 150 843441AM-300 8 SOIC 300 Block Diagrams FemtoClock PLLOSC nPLL_SEL 25MHz XTAL XTAL_IN XTAL _OUT 00 = 75MHz 01 = 100MHz 10 = 150MHz (default) 11 = 300MHz Q nQ SSC_SEL(1:0) F_S E L( 1: 0) SSC Output Control Logic 16- Lead TSSOP FemtoClock PLL OSC25MHz XTAL XTAL_IN XTAL _OUT Q nQ SSC_SEL(1:0) SSC Output Control Logic 8- Lead SOIC Pulldown Pullup: Pulldown Pulldown: Pulldown Pulldown:Pulldown Pin Assignments nc SSC_SEL0 XTAL_IN XTAL_OUT VEE F_SEL1 nPLL_SEL nQ Q VCC F_SEL0 VCCSSC_SEL1 VEE nc nc 843441 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 843441 8-Lead SOIC, 150 Mil 3.90mm x 4.90mm x 1.375mm package body M Package Top View 843441-150 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 843441 Data Sheet FemtoClock® SAS/SATA Clock Generator
843441 Data Sheet
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics XTAL_IN Input Pullup Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. 5V CC Power Power supply pin. 6, 7 Q, nQ Output Differential clock outputs. LVPECL interface levels. 8V EE Power Negative supply pin. 1, 15 V EE Power Negative supply pins. XTAL_IN Input Pullup Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. 5, 6, 7 nc Unused No connect pins. 9, 11 V CC Power Power supply pins. 10 F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. 12, 13 Q, nQ Output Differential clock outputs. LVPECL interface levels. 14 nPLL_SEL Input Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels. 16 F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
3©2016 Integrated Device Technology, Inc June 30, 2016 Table 3A. SSC_SEL[1:0] Function Table Table 3B. F_SEL[1:0] Function Table Table 3B applicable only for 16 Lead TSSOP package. Inputs ModeSSC_SEL1 SSC_SEL0 0 (default) 0 (default) SSC Off 0 1 0.60% Down-spread 1 0 0.30% Down-spread 1 1 0.33% Center-spread Inputs Output Frequency (MHz)F_SEL1 F_SEL0 00 7 5 01 1 0 0 1 (default) 0 (default) 150 11 3 0 0
4©2016 Integrated Device Technology, Inc June 30, 2016 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C NOTE 1: Output termination with 50 to VCC – 2V. Item Rating Supply Voltage, VCC 4.6V Inputs, VI, (LVCMOS) XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA
16 Lead TSSOP
8 Lead SOIC
81.2°C/W (0 mps) 96.0°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 66 mA Symbol Parameter Test Conditio ns Minimum Typic al Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current F_SEL1 V CC = VIN = 3.465V 5 µA SSC_SEL[0:1], F_SEL0, nPLL_SEL VCC = VIN = 3.465V 150 µA IIL Input Low Current F_SEL1 V CC = 3.465V, VIN = 0V -150 µA SSC_SEL[0:1], F_SEL0, nPLL_SEL VCC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CC – 1.4 V CC – 0.9 V VOL Output Low Voltage; NOTE 1 V CC – 2.0 V CC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 0.9 V
Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C NOTE: Using a 25MHz, 18pF quartz crystal. has been reached under these conditions. NOTE 1: Please refer to the Phase Noise plots. NOTE 2: Refer to Application Section for peak-to-peak jitter calculations. NOTE 3: Tested per JEDEC 65B.
6©2016 Integrated Device Technology, Inc June 30, 2016 Typical Phase Noise at 100MHz NOTE: Measured on Aeroflex PN9000 Noise Power dBc Hz Offset Frequency (Hz) 100MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.39ps (typical)
7©2016 Integrated Device Technology, Inc June 30, 2016 Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Rise/Fall Time Cycle-to-Cycle Jitter RMS Phase Jitter Output Duty Cycle/Pulse Width/Period RMS Period Jitter, Peak-to-Peak SCOPE Qx nQx VEE VCC -1.3V ± 0.165V nQ Q tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Q nQ Q VOH VREF VOL Mean Period (First edge after trigger) 10,000 cycles Reference Point (Trigger Edge) Histogram t jit (pk-pk)
8©2016 Integrated Device Technology, Inc June 30, 2016 Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC XTAL_OUT XTAL_IN 100 100 Zo = 50 ohmsRsRo Zo = Ro + Rs .1uf LVCMOS Driver XTAL_OU T XTAL_I N Zo = 50 ohms C2 .1uf LVPECL Driver Zo = 50 ohms 50R3
9©2016 Integrated Device Technology, Inc June 30, 2016 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
and C2 = 27pF are recommended for frequency accuracy. used. This will required adjusting C1 and C2. power supplies to isolate noise from coupling into the internal PLL. filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. be adjusted and if required, additional filtering be added. Figure 3. 843441 Schematic Example
11©2016 Integrated Device Technology, Inc June 30, 2016 Peak-to-Peak Jitter Calculations A standard deviation of a statistical population or data set is the square root of its variance. A standard deviation is used to calculate the probability of an anomaly or to predict a failure. Many times, the term "root mean square" (RMS) is used synonymously for standard deviation. This is accurate when referring to the square root of the mean squared deviation of a signal from a given baseline and the data set contains a Gaussian distribution with no deterministic components. A low standard deviation indicates that the data set tends to be close to the mean with little variation. A large standard deviation indicates that the data set is spread out and has a large variation from the mean. A standard deviation is required when calculating peak-to-peak jitter. Since true peak-to-peak jitter is random and unbounded, it is important to always associate a bit error ratio (BER) when specifying a peak-to-peak jitter limit. Without it, the specification is meaningless. Given that a BER is application specific, many frequency timing devices specify jitter as an RMS. This allows the peak-to-peak jitter to be calculated for the specific application and BER requirement. Because a standard deviation is the variation from the mean of the data set, it is important to always calculate the peak-to-peak jitter using the typical RMS value. The table shows the BER with its appropriate RMS Multiplier. Once the BER is chosen, the peak to peak jitter can be calculated by simply multiplying the RMS multiplier with the typical RMS datasheet specification. For example, if a 10 -12 BER is required, multiply 14.260 times the typical jitter specification. Jitter (peak-to-peak) = RMS Multiplier x RMS (typical) This calculation is not specific to one type of Jitter classification. It can be used to calculate BER on various types of RMS jitter. It is important that the user understands their jitter requirement to ensure they are calculating the correct BER for their jitter requirement. BER RMS Multiplier 10-3 6.582 10-4 7.782 10-5 8.834 10-6 9.784 10-7 10.654 10-8 11.462 10-9 12.218 10-10 12.934 10-11 13.614 10-12 14.260 10-13 14.882 10-14 15.478 10-15 16.028
12©2016 Integrated Device Technology, Inc June 30, 2016 This section provides information on power dissipation and junction temperature for the 843441. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843441 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 66mA = 228.69mW Power (outputs) MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 228.69mW + 30mW = 258.69mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96°C/W per Table 6B below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.259W * 96°C/W = 94.864°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W JA vs. Air Flow Linear Feet per Second 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
14©2016 Integrated Device Technology, Inc June 30, 2016 Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC Transistor Count The transistor count for 843441 is: 6303 JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W JA vs. Air Flow Linear Feet per Second 02 0 0 5 0 0 Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
15©2016 Integrated Device Technology, Inc June 30, 2016 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 8A. Package Dimensions for 16 Lead TSSOP Reference Document: JEDEC Publication 95, MO-153 Package Outline - M Suffix for 8 Lead SOIC Table 8B. Package Dimensions for 8 Lead SOIC Reference Document: JEDEC Publication 95, MS-012 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0° 8° aaa 0.10 All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0° 8°
16©2016 Integrated Device Technology, Inc June 30, 2016
Ordering Information
Table 9. Ordering Information
17©2016 Integrated Device Technology, Inc June 30, 2016 Rev Table Page Description of Change Date A T3A 3 SSC_SEL Function Table - updated Mode column. 5/18/11 A Removed ICS from part number where needed. Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Updated header and footer 6/30/16
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA www.IDT.com 18©2016 Integrated Device Technology, Inc June 30, 2016