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Technical content
Features
- Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs
- Using a 25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
- VCO range: 520MHz – 680MHz
- RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.3ps (typical)
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package DIV_SELB0 VCO_SEL MR QA nQA OEB OEA FB _DIV DIV_SELA0 DIV_SELB1 nQB0 QB0 nQB1 QB1 XTAL _SEL REF_ CLK XTAL _IN XTAL _OUT VEE DIV_SELA1 VCCO_A VCCA VCC V CCO_B Pin Assignment 8433625 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View 8433625 Datasheet FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
2©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016
8433625 Datasheet
XTAL_IN Xtal Osc 00 = ÷1 01 = ÷2 10 = ÷4 11 = ÷5 (default) OEA MR OEB FemtoClock VCO Pullup Pullup Pullup Pullup Pullup Pulldown Pulldown Pullup: Pulldown Pulldown XTAL_SEL DIV_SELA[1:0] REF_CLK DIV_SELB[1:0] FB_DIV XTAL_OUT VCO_SEL QA nQA QB0 nQB0 QB1 nQB1 00 = ÷1 01 = ÷2 10 = ÷4(default) 11 = ÷5 0 = ÷25(default) 1 = ÷24
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1 DIV_SELB0 Input Pullup Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
2 VCO_SEL Input Pullup
dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels.
3 MR Input Pulldown
resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. CCO_A Power Output supply pin for Bank A outputs. 5, 6 QA, nQA Output Differential output pair. LVPECL interface levels.
7 OEB Input Pullup
state of outputs are enabled. LVCMOS/LVTTL interface levels.
8 OEA Input Pullup
are enabled. LVCMOS/LVTTL interface levels. HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels. 10 V CCA Power Analog supply pin. 11 V CC Power Core supply pin. 12 DIV_SELA0 Input Pulldown Division select pin for Bank A. Default = LOW. LVCMOS/LVTTL interface levels. 13 DIV_SELA1 Input Pullup Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels. 14 V EE Power Negative supply pin.
16 XTAL_OUT,
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. single-ended reference clock. 17 REF_CLK Input Pulldown Single-ended reference clock input. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels.
18 XTAL_SEL Input Pullup
Crystal select pin. Selects between the single-ended REF_CLK or crystal interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. 19, 20 nQB1, QB1 Output Differential out put pair. LVPECL interface levels. 21, 22 nQB0, QB0 Output Differential out put pair. LVPECL interface levels. 23 V CCO_B Power Output supply pin for Bank B outputs. 24 DIV_SELB1 Input Pullup Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
Table 2. Pin Characteristics
Figure 1. OE Timing Diagram NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability.
NOTE 1: Outputs termination with 50 to VCCO_A, _B – 2V. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
Table 6. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 0.3V, VEE = 0V, TA = 0°C to 70°C has been reached under these conditions. NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016 Typical Phase Noise at 156.25MHz Typical Phase Noise at 312.5MHz 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.30ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 312.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.12ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
9©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016 Parameter Measurement Information LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Output Skew Bank Skew Output Rise/Fall Time VCC, -1.3V ± 0.3V VCCA VCCO_A, VCCO_B nQA, nQB0, nQB1 QA, QB0, QB1 nQx Qx nQy Qy nQB0 QB0 nQB1 QB1 tsk(b) nQA, nQB[0:1] QA, QB[0:1]
10©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 8433625 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO_x should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. Figure 2. Power Supply Filtering resistor can be tied from the REF_CLK to ground. resistance is not required but can be added for additional protection. should either be left floating or terminated.
crystal and were chosen to minimize the ppm error. Figure 3. Crystal Input Interface Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
12©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016 Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
example, the device is operated at VCC = VCCO_A = VCCO_B = 3.3V. approaches are shown in the LVPECL Termination Application Note. Figure 6. 8433625 Schematic Example
This section provides information on power dissipation and junction temperature for the 8433625. Equations and example calculations are also provided. The total power dissipation for the 8433625 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for devices is 125°C. a multi-layer board, the appropriate value is 82.3°C/W per Table 7 below. Table 7. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP
17©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016
Ordering Information
Table 10. Ordering Information
18©2016 Integrated Device Technology, Inc. Revision B, February 2, 2016 Rev Table Page Description of Change Date B T10 Section , “General Description” - deleted HiperClocks logo. Ordering Information Table - deleted Tape & Reel count. Deleted all HiperClocks references throughout the datasheet. Deleted ICS prefix from part number throughout the datasheet. Updated datasheet header/footer. 1/20/16
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