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Technical content
Features
- Fully integrated PLL, no external loop filter requirements
- One differential 3.3V LVPECL output
- Crystal oscillator interface: 10MHz to 25MHz
- Output frequency range: 31.25MHz to 720MHz
- VCO range: 250MHz to 720MHz
- Parallel or serial interface for programming M and N dividers during power-up
- RMS period jitter: 6ps (maximum)
- Cycle-to-cycle jitter: 40ps (maximum)
- 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) packages Block Diagram 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 S_CLOCK S_DATA S_LOAD VCCA VCCA FREF_EXT XTAL_SEL XTAL1 nc XTAL2 OE nP_LOAD nc FOUT nFOUT VEE VCC VCC TEST VEE VCC 5 6 7 8 9 10 11 25 24 23 22 21 20 19 S_CLOCK S_DATA S_LOAD VCCA FREF_EXT XTAL_SEL XTAL1 XTAL2 OE nP_LOAD M3 VEE VCC VEE TEST nFOUT FOUT VCC Pin Assignments ICS84330CI
32 Lead LQFP
7mm x 7mm x 1.4mm package body Top View ICS84330CI
28 Lead PLCC
11.6mm x 11.4mm x 4.1mm package body Top View 720MHz, Low Jitter, Crystal-to-LVPECL Frequency Synthesizer 84330CI Data Sheet
Characteristics, T able 6, NOTE 1. M divider is also applied to the phase detector. buffers. The divider provides a 50% output duty cycle. 000 (shift register out) when operating in the parallel input mode.
- The frequency out is defined as follows:
001 H I G H f OUT
101 L O W f OUT
Figure 1. Parallel & Serial Load Operations
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics VCCA Power Analog supply pin. XTAL1, XTAL2 Crystal oscillator in terface. XTAL1 is an oscillator input, XTAL2 is an oscillator output. Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW. LVCMOS / LVTTL interface levels. OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. N0, N1 Input Pullup Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. VEE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. Single-ended LVPECL interface levels. nFOUT, FOUT Output Differenti al output for the synthesizer. 3.3V LVPECL interface levels. FREF_EXT Input Pulldown PLL reference input. LVCMOS / LVTTL interface levels. rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS / LVTTL interface levels.
4©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Function Tables Table 3A. Parallel and Serial Mode Function Table NOTE: L = LOW H = HIGH X = Don’t care = Rising edge transition = Falling edge transition Table 3B. Programmable VCO Frequency Function Table NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. Table 3C. Programmable Output DividerFunction Table Inputs ConditionsnP_LOAD M N S_LOAD S_CLOCK S_DATA X X X X X X Reset. M and N bits are all set HIGH. L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST mode 000. Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. HX XL Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. HX X LD a t a Contents of the shift register are passed to the M divider and N output divider. HX X L Data M divider and N output divider values are latched. H X X L X X Parallel or serial input do not affect shift registers. HX X H Data S_DATA passed directly to M divider as it is clocked. VCO Frequency (MHz) M Divide 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 2 5 001111101 2 5 2 1 2 6 001111110 2 5 4 1 2 7 001111101 2 5 6 1 2 8 010000010 7 1 8 3 5 9 101100111 7 2 0 3 6 0 101101000 Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 00 21 2 5 3 6 0 01 46 2 . 5 1 8 0 1 0 8 31.25 90 11 12 5 0 7 2 0
5©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVPECL DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VCC -2V. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 37.8C/W (0 lfpm) 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 160 mA ICCA Analog Supply Current 17 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current M0-M8, N0, N1, OE, nP_LOAD, XTAL_SEL VCC = VIN = 3.465V 5 µA S_LOAD, S_CLOCK FREF_EXT, S_DATA VCC = VIN = 3.465V 150 µA IIL Input Low Current M0-M8, N0, n1, OE, nP_LOAD, XTAL_SEL VCC = 3.465V, VIN = 0V -150 µA S_LOAD, S_CLOCK FREF_EXT, S_DATA VCC = 3.465V, VIN = 0V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CC - 1.4 V CC - 0.9 V VOL Output Low Voltage; NOTE 1 V CC - 2.0 V CC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Table 5. Crystal Characteristics Table 6. Input Frequency Characteristics, VCC = 3V±5%, VEE = 0V, TA = -40°C to 85°C valid values of M are 80 M 230. recommendations on optimizing the performance using the FREF_EXT input. Table 7. AC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. See Parameter Measurement Information section. NOTE: Characterized using 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications section.
7©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Parameter Measurement Information 3.3/3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Rise/Fall Time Period Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC, -1.3V±0.165V VCCA tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
(First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nFOUT FOUT
10©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
11©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Layout Guideline The schematic of the 84330CI layout example used in this layout guideline is shown in Figure 6A. The 84330CI recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. Figure 6A. 84330CI Schematic of Recommended Layout RU7 RD7 SP RD1 RU9 SP Zo = 50 Ohm RD9 VCC VCC C11 0.01u VCC=3.3V VCCA OE SP nPLoad Zo = 50 Ohm RD8 SP RD6 0.1uF RU10 VCC RU1 SP N[1:0] =00 (Divide by 2) RU8 Fout = 200 MHz 16MHz, 18pF OE C16 10u RU0 SP RU12 C1SP 0.1u SP = Space (i.e. not ints talled) RU11 SP RD10 SP RD12 SP RD0 ICS84330 28VCCA FREF_EX T XTAL_SEL X_I N X_OUT OE nP_LOAD VEE TEST S_DATA S_CLOCK VCC FOUT nFOUT VEE VCC S_LOAD nPLOAD
12©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors C3 and C4, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
- The differential 50 output traces should have the same length.
- Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
- Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
- To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
- Make sure no other signal traces are routed between the clock trace pair.
- The matching termination resistors should be located as close to the receiver input pins as possible. Crystal The crystal X1 should be located as close as possible to the pins 4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. Figure 6B. 84330CI PCB Board Layout for 84330CI Signals Traces VCCA VCC
50 Ohm
13©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 84330CI. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 84330CI is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 17mA = 58.9mW Power (outputs) MAX = 30mW/Loaded Output Pair Total Power_MAX (3.465V, with all outputs switching) = 58.9mW + 30mW = 88.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8A. Thermal Resistance JA for 28 Lead PLCC, Forced Convection Table 8B. Thermal Resistance JA for 32 Lead LQFP, Forced Convection JA by Velocity Linear Feet per Minute 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W JA by Velocity Linear Feet per Minute 02 0 0 5 0 0 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
15©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Reliability Information Table 9A. JA vs. Air Flow Table for a 28 Lead PLCC Table 9B. JA vs. Air Flow Table for a 32 Lead LQFP Transistor Count The transistor count for 84330CI is: 4498 JA vs. Air Flow Linear Feet per Minute 02 0 0 5 0 0 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W JA vs. Air Flow Linear Feet per Minute 02 0 0 5 0 0 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
16©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Package Outline and Package Dimensions Package Outline - V Suffix for 28 Lead PLCC Table 10A. Package Dimensions for 28 Lead PLCC Reference Document: JEDEC Publication 95, MS-018 JEDEC Variation All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D/E 12.32 12.57 D1/E1 11.43 11.58 D2/E2 5.21 5.46
17©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Package Outline - Y Suffix for 32 Lead LQFP Table 10B. Package Dimensions for 32 Lead LQFP Reference Document: JEDEC Publication 95, MS-026 JEDEC Variation: BBA All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 0° 7° ccc 0.10
18©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet
Ordering Information
Table 11. Ordering Information
19©2016 Integrated Device Technology, Inc Revision A January 13, 2016 84330CI Data Sheet Revision History Sheet Rev Table Page Description of Change Date A 1 Features Section - corrected Output Frequ ency Range from 25MHz to 31.25MHz. 12/7/04 A T10A Added Recommendations for Unused Input and Output Pins. Package Dimension Table - D2/E2 changed the min. from 4.85 to 5.21 and the max. from 5.56 to 5.46. Converted datasheet format. 2/2/09 A T7 6 AC Characteristics Table - due to datasheet format conversion, corrected cycle-to-cycle test conditions back to original conditions. Updated Overdriving the XTAL Interface. Updated new Header/Footer format. 1/7/11 A T11 18 Removed leaded orderables from Ordering Information table 11/29/12 A T11 Features section - removed leaded part reference. Ordering Information - Removed quantities in Tape and Reel and removed the Lead Free note below the table. Removed ICS from part numbers. Updated data sheet header and footer. 1/13/16
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