84330-01 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 20
Technical content
Features
- Fully integrated PLL, no external loop filter requirements
- One differential 3.3V LVPECL output
- Crystal oscillator interface: 10MHz – 25MHz
- Output frequency range: 31.25MHz – 700MHz
- VCO range: 250MHz – 700MHz
- Parallel or serial interface for programming M and N dividers during power-up
- RMS period jitter: 5ps (maximum)
- Cycle-to-cycle jitter: 40ps (maximum)
- 3.3V supply voltage
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- For functional replacement part use 8T49N242 nP_LOAD VCC XTAL_OUT XTAL_IN nc nc VCCA V EE TEST VCC S_LOAD S_DATA S_CLOCK VCCO FOUT nFOUT VEE Pin Assignments 84330-01
28 Lead SOIC
7.5mm x 18.05mm x 2.25mm package body M Package Top View 5 6 7 8 9 10 11 25 24 23 22 21 20 19 S_CLOCK S_DATA S_LOAD VCCA nc nc XTAL_IN XTAL_OUT VCC nP_LOAD M3 VEE VCC VEE TEST nFOUT FOUT VCCO 84330-01
28 Lead PLCC
11.5mm x 11.5mm x 4.4mm package body V Package Top View Block Diagram FOUT nFOUT OSC XTAL_IN XTAL_OUT S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL TEST CONFIGURATION INTERFACE LOGIC ÷1 6 PHASE DETECTOR ÷1 0÷2 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (84330CV-01)
Characteristics, Table 5, NOTE 1. buffers. The divider provides a 50% output duty cycle.
101 L O W f O U T
Figure 1. Parallel & Serial Load Operations
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Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics M5, M6, M7, M8 Input Pullup M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. N0, N1 Input Pullup Determines output divider value as defined in Table 3C, Function Table. LVCMOS/LVTTL interface levels. VEE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. Single-ended LVPECL interface levels. FOUT, nFOUT Output Differential output pair for the synthesizer. LVPECL interface levels. VCCO Power Output supply pi n for LVPECL outputs. S_CLOCK. LVCMOS/LVTTL interface levels. S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS/LVTTL interface levels. VCCA Power Analog supply pin. XTAL_OUT Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL interface levels.
Rev A 5/26/16 4 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 84330-01 DATA SHEET Function Tables Table 3A. Parallel and Serial Mode Function Table NOTE: L = LOW H = HIGH X = Don’t care = Rising edge transition = Falling edge transition Table 3B. Programmable VCO Frequency Function Table NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz. Inputs ConditionsnP_LOAD M N S_LOAD S_CLOCK S_DATA X X X X X X Reset. M and N bits are all set HIGH. L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST mode 000. Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. HX XL Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. HX X LD a t a Contents of the shift register are passed to the M divider and N output divider. HX X L Data M divider and N output divider values are latched. H X X L X X Parallel or serial input do not affect shift registers. HX XH Data S_DATA passed directly to M divider as it is clocked. VCO Frequency (MHz) M Divide 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 2 5 001111101 2 5 2 1 2 6 001111110 2 5 4 1 2 7 001111101 2 5 6 1 2 8 010000010 6 9 6 3 4 8 101011100 6 9 8 3 4 9 101011101 7 0 0 3 5 0 101011110
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
5 Rev A 5/26/16
Table 3C. Programmable Output DividerFunction Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 002 1 2 5 3 5 0 014 6 2 . 5 1 7 5 1 0 8 31.25 87.5 111 2 5 0 7 0 0 Item Rating Supply Voltage, V CC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 57C/W (0 mps) 45.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 160 mA ICCA Analog Supply Current 16 mA
NOTE 1: Outputs terminated with 50 to VCCO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 5. Input Frequency Characteristics, VCC = VCCA = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C 25MHz, valid values of M are 80 M 224. Table 6. Crystal Characteristics
Table 7. AC Characteristics, VCC = VCCA = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C to 70°C See Parameter Measurement Information section. Characterized using XTAL inputs. has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications Section.
Rev A 5/26/16 8 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 84330-01 DATA SHEET Parameter Measurement Information 3.3/3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Rise/Fall Time Period Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC, VCCO VCCA, -1.3V±0.165V tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
(First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nFOUT FOUT
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
9 Rev A 5/26/16
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 84330-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. The 10 resistor can also be replaced by a ferrite bead. Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: TEST Output The unused TEST output can be left floating. There should be no trace attached. LVPECL Output All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. VCC VCCA 3.3V 10µF0.01µF 0.01µF
11 Rev A 5/26/16
Figure 5. Cycle-to-Cycle Jitter vs. fOUT (using a 16MHz crystal) recommended only as guidelines. to maximize operating frequency and minimize signal distortion. component process variations.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
13 Rev A 5/26/16
This section provides information on power dissipation and junction temperature for the 84330-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 84330-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 160mA = 554.4mW Power (outputs) MAX = 30mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 554.4mW + 30mW = 584.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 57°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.584W * 57°C/W = 103.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8A. Thermal Resistance JA for 28 Lead SOIC, Forced Convection Table 8B. Thermal Resistance JA for 28 Lead PLCC, Forced Convection JA by Velocity Meters per Second 0 Multi-Layer PCB, JEDEC Standard Test Boards 57°C/W JA by Velocity Meters per Second 0 Multi-Layer PCB, JEDEC Standard Test Boards 45.7°C/W
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 8. Figure 8. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
15 Rev A 5/26/16
Table 9A. JA vs. Air Flow Table for a 28 Lead SOIC Table 9B. JA vs. Air Flow Table for a 28 Lead PLCC Transistor Count The transistor count for 84330-01 is: 4498 Pin compatible with the SY89430V Package Outline and Package Dimensions Package Outline - M Suffix for 28 Lead SOIC Table 10A. Package Dimensions for 28 Lead SOIC Reference Document: JEDEC Publication 95, MS-013, MS-119 JA vs. Air Flow Meters per Second 0 Multi-Layer PCB, JEDEC Standard Test Boards 57°C/W JA vs. Air Flow Meters per Second 0 Multi-Layer PCB, JEDEC Standard Test Boards 45.7°C/W JEDEC: 300 MIL All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 17.70 18.40 E 7.40 7.60 e 1.27 Basic H 10.0 10.65 h 0.25 0.75 L 0.40 1.27 0° 8°
Rev A 5/26/16 16 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 84330-01 DATA SHEET Package Outline - V Suffix for 28 Lead PLCC Table 10B. Package Dimensions for 28 Lead PLCC Reference Document: JEDEC Publication 95, MS-018 JEDEC All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D & E 12.32 12.57 D1 & E1 11.43 11.58 D2 & E2 4.85 5.56
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
17 Rev A 5/26/16
Ordering Information
Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
18 Rev A 5/26/16
Rev Table Page Description of Change Date A T11 Updated Overdriving the XTAL Interface section. Ordering Information - Added “Lead Free” Marking to lead-free 28 Lead SOIC. Updated head/footer throughout the datasheet. 2/23/10 Updated data sheet format. 4/22/15 A Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 5/26/16
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