84330AV-02LF

84330-02 RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
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700MHz, Low Jitter, Crystal-to-3.3V Differential LVPECL Frequency Synthesizer 84330-02 Data Sheet ©2016 Integrated Device Technology, Inc Revision B May 26, 20161 GENERAL DESCRIPTION The 84330-02 is a general purpose, single output high frequency synthesizer. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and8. Output frequency steps from 250kHz to 2MHz canbe achiev-ed using a 16MHz crystal depending on the output divider setting.

FEATURES

• Fully integrated PLL, no external loop fi lter requirements
• 1 differential 3.3V LVPECL output
• Crystal oscillator interface: 10MHz to 25MHz
• Output frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming M and N divid- ers during power-up
• RMS Period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
• Industrial temperature information available upon request
• For functional replacement part use 8T49N242 PIN ASSIGNMENTBLOCK DIAGRAM PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017

can be used to program the M and N bits and test bits T2:T0. Frequency Characteristics, Table 6, NOTE 1. requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS NOTE: nP_LOAD is designed to eliminate runt pulses when changing M and N bits.

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS VCCA Power Analog supply pin. Crystal oscillator interface. XTAL_IN is an oscillator input. XTAL_OUT is an oscillator output. source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW. LVCMOS / LVTTL interface levels. OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. M divider, and when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. MOS / LVTTL interface levels. N0, N1 Input Pullup Determines N output divider value as defi ned in Table 3C Function Table. LVCMOS / LVTTL interface levels. EE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. nFOUT, FOUT Output Differential output for the synthesizer. 3.3V LVPECL interface levels. FREF_EXT Input Pulldown PLL reference input. LVCMOS / LVTTL interface levels. rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

©2016 Integrated Device Technology, Inc Revision B May 26, 20164 TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs Conditions nP_LOAD M N S_LOAD S_CLOCK S_DATA L Data Data X X X Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. HX X L ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. HX X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. HX X ↓ L Data M divide and N output divide values are latched. H X X L X X Parallel or serial input do not affect shift registers. HX X H Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 2 5 001111101 2 5 2 1 2 6 001111110 2 5 4 1 2 7 001111111 2 5 6 1 2 8 010000000 6 9 6 3 4 8 101011100 6 9 8 3 4 9 101011101 7 0 0 3 5 0 101011110 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 2 125 350 0 1 4 62.5 175 1 0 8 31.25 87.5 1 1 1 250 700

©2016 Integrated Device Technology, Inc Revision B May 26, 20165 TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CC - 1.4 V CC - 0.9 V VOL Output Low Voltage; NOTE 1 V CC - 2.0 V CC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 130 mA ICCA Analog Supply Current 15 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current M0-M8, N0, N1, OE, nP_LOAD, XTAL_ SEL V CC = VIN = 3.465V 5 µA S_LOAD, S_CLOCK FREF_EXT, S_DATA VCC = VIN = 3.465V 150 µA IIL Input Low Current M0-M8, N0, N1, OE, nP_LOAD, XTAL_ SEL V CC = 3.465V, VIN = 0V -150 µA S_LOAD, S_CLOCK FREF_EXT, S_DATA VCC = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 2.6 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCC/2. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 37.8°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511. Using the maximum frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224. Section for recommendations on optimizing the performance using the FREF_EXT input. TABLE 5. CRYSTAL CHARACTERISTICS TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C See Parameter Measurement Information section. Characterized using a XTAL input. NOTE 2: See Applications section.

©2016 Integrated Device Technology, Inc Revision B May 26, 20167 PARAMETER MEASUREMENT INFORMATION CYCLE-TO-CYCLE JITTER PERIOD JITTER3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

©2016 Integrated Device Technology, Inc Revision B May 26, 20168 The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 84330-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be connected to each V CCA pin. FIGURE 2. POWER SUPPLY FILTERING 10Ω VCCA 10μF .01μF 3.3V .01μF VCC POWER SUPPLY FILTERING TECHNIQUES

©2016 Integrated Device Technology, Inc Revision B May 26, 201610 The schematic of the 84330-02 layout example used in this layout guideline is shown in Figure 6A. The 84330-02 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general LAYOUT GUIDELINE FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. ICS84330-02 28VCCA FREF_EX T XTAL_SEL X_I N X_OUT OE nP_LOAD VEE TEST S_DATA S_CLOCK VCC FOUT nFOUT VEE VCC S_LOAD Zo = 50 Ohm RD1 Fout = 200 MHzRU7 VCC M1 RU1 SP OE C16 10u RD0 RD10 SP RD12 SP RU9 SP RU8 VCC C1SP 0.1uF 0.1u RD7 SP VCC RD6 nPLOAD SP = Space (i.e. not ints talled) C11 0.01u VCCA RD8 SP N[1:0] =00 (Divide by 2) RU0 SP RD9 Zo = 50 Ohm 16MHz, 18pF OE RU11 SP SP RU12 nPLoad VCC=3.3V RU10

©2016 Integrated Device Technology, Inc Revision B May 26, 201611 FIGURE 6B. PCB BOARD LAYOUT FOR 84330-02 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C3 and C4, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have the same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 9. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION This section provides information on power dissipation and junction temperature for the 84330-02. Equations and example calculations are also provided. The total power dissipation for the 84330-02 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 145mA = 502.4mW
• Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 502.4mW + 30mW = 532.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 9 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 8. termination voltage of VCC- 2V.

• For logic high, V OUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX - VOH_MAX) = 0.9V
• For logic low, V OUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 10. θJAVS. AIR FLOW PLCC TABLE FOR 28 LEAD PLCC

TABLE 11. PACKAGE DIMENSIONS

TABLE 12. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision B May 26, 201618 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T12 17 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/25/10 B T12 17 Remove ICS from the part number where needed. Ordering Information - removed leaded part numbers, 500 from tape and reel and the note below the table. Updated headers and footers. 1/14/16 B Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 5/26/16

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