ICS843301I-108 IDT | Alldatasheet

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FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL 75MHZ FREQUENCY SYNTHESIZER W/SSC ICS843301I-108 IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 1 ICS843301BGI-108 REV. A OCTOBER 9, 2007 PRELIMINARY GENERAL DESCRIPTION The ICS843301I-108 is a 75MHz Frequency Generator and a member of the HiPerClocks TM family of high performance devices from IDT. The ICS843301I-108 uses a 20MHz crystal to synthesize 75MHz output. The device supports 0.5% downspread spread spectrum clocking. The ICS843301I- 108 has excellent <1ps phase jitter performance, over an integration range of 900kHz - 7.5MHz . The device is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.

FEATURES

  • One differential 3.3V or 2.5V LVPECL output
  • Crystal oscillator interface designed for 20MHz, 18pF parallel resonant crystal
  • Output frequency: 75MHz
  • Supports SSC, 0.5% downspread
  • RMS phase jitter @ 75MHz, using a 20MHz crystal (900kHz - 7.5MHz): 0.73ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ SSC BLOCK DIAGRAM PIN ASSIGNMENT OSC Phase Detector VCO 600MHz N Div M Div ÷30 PLLXTAL_IN XTAL_OUT Q nQ 20MHz SSC FUNCTION TABLE tupnI edoMCSS )tluafed(0f fOCSS 1d aerpsnwoD%5.0 SSC Pulldown ICS843301I-108 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS

IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 3 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HO 1ETON;egatloVhgiHtuptuOV CC 4.1-V CC 9.0-V V LO 1ETON;egatloVwoLtuptuOV CC 0.2-V CC 7.1-V V GNIWS gniwSegatloVtuptuOkaeP-ot-kaeP6 .00 .1V 05htiwdetanimretstuptuO:1ETON Ω Vot CC .V2- lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanAV CC 01.0–3 .3V CC V I ACC tnerruCylppuSgolanA 01A m I EE tnerruCylppuSrewoP 601A m TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 573.25 .25 26.2V V ACC egatloVylppuSgolanAV CC 90.0–5 .2V CC V I ACC tnerruCylppuSgolanA 9A m I EE tnerruCylppuSrewoP 001A m TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI V CC V3.3=2 V CC 3.0+V V CC V5.2=7 .1V CC 3.0+V V LI egatloVwoLtupnI V CC V3.3=3 .0-8 .0V V CC V5.2=3 .0-7 .0V I HI tnerruChgiHtupnIV CC V= NI V526.2roV564.3=0 51A µ I LI tnerruCwoLtupnIV CC V,V526.2roV564.3= NI V0=5 -A µ

TABLE 4. CRYSTAL CHARACTERISTICS

IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 5 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx nQx LVPECL VEE -1.3V ± 0.165V Clock Outputs 20% 80% 80% 20% tR tF VSWING tPW tPERIOD tPW tPERIOD odc = x 100% Q nQ VCC 2.5V OUTPUT LOAD AC TEST CIRCUIT VCCA VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram PERIOD JITTER SCOPE Qx nQx LVPECL VEE -0.5V ± 0.125V VCC VCCA

IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 8 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω FOUT FIN RTT = Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V 125Ω 125Ω 84Ω 84Ω Zo = 50Ω Zo = 50Ω FOUT FIN The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR 3.3V LVPECL OUTPUT FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION

This section provides information on power dissipation and junction temperature for the ICS843301I-108. Equations and example calculations are also provided. The total power dissipation for the ICS843301I-108 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 106mA = 367.29mW
  • Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.465V , with all outputs switching) = 370.75mW + 30mW = 397.29mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 8-PIN TSSOP, FORCED CONVECTION

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 7. θ

TABLE 8. PACKAGE DIMENSIONS

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION

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Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY