8432CYI-51LF

8432I-51 RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
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Technical content

700MHz, Crystal-to-3.3V Differential LVPECL Frequency Synthesizer 8432I-51 DATA SHEET 8432I-51 REVISION A 11/18/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 8432I-51 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency Synthesizer. The 8432I-51 has a selectable REF_CLK or crystal input. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be pro- grammed using the serial or parallel interface to the confi guration logic. The low phase noise characteristics of the 8432I-51 make it an ideal clock source for Gigabit Ethernet, Fibre Channel 1 and 2, and Infi niband applications. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 12MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter: 3.5ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_OUT REF_CLK XTAL_SEL V CCA S_LOAD S_DATA S_CLOCK MR nc V EE VEE nFOUT0 FOUT0 V CCO nFOUT1 FOUT1 V CC TEST XTAL_IN nP_LOAD VCO_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 8432I-51 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View

2 REVISION B 11/18/15

in Table 3B, Programmable VCO Frequency Function Table. the M divider and N output divider on each ris-ing edge of S_CLOCK. Frequency Characteristics, Table 5, NOTE 1. quires no external components for setting the loop bandwidth. lator. The output of the oscillator is fed into the phase detector. buffers. The divider provides a 50% output duty cycle. and N1 is passed directly to the M divider and N output divider. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed.

TABLE 1. PIN DESCRIPTIONS

1 M5 Input Pullup

of nP_LOAD input. LVCMOS / LVTTL interface levels. Function Table. LVCMOS / LVTTL interface levels. driven LOW in parallel mode. LVCMOS / LVTTL interface levels. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interface levels.

17 MR Input Pulldown

M, N, and T values. LVCMOS / LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register

on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. CLOCK. LVCMOS / LVTTL interface levels. MOS / LVTTL interface levels.

22 XTAL_SEL Input Pullup

Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW. LVCMOS / LVTTL interface levels. 23 REF_CLK Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels. IN Input Crystal oscillator interface. XTAL_IN is the input. N output divider value. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

4 REVISION B 11/18/15

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LH X X H ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 1 250 700 0 1 2 125 350 1 0 4 62.5 175 1 1 8 31.25 87.5 VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 0 000001010 2 7 5 1 1 000001011 6 5 0 2 6 000011010 6 7 5 2 7 000011011 7 0 0 2 8 000011100 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz.

5 700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, V EE = 0V, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, V EE = 0V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 CC + 0.3 V REF_CLK 2 V CC + 0.3 V V IL Input Low Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 -0.3 0.8 V REF_CLK -0.3 1.3 V I IH Input High Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, REF_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = V IN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL V CC = V IN = 3.465V 5 µA I IL Input Low Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, REF_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = 3.465V, V IN = 0V -5 µA M5, XTAL_SEL, VCO_SEL V CC = 3.465V, V IN = 0V -150 µA V OH Output High Voltage TEST; NOTE 1 2.6 V V OL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to V CCO /2. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.15 3.3 3.465 V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 145 mA I CCA Analog Supply Current 15 mA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 32 Lead LQFP 47.9°C/W (0 lfpm) 32 Lead VFQFN 41.07°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability.

6 REVISION B 11/18/15

fi gure “3.3V Output Load Test Circuit”. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V mum frequency of 25MHz, valid values of M are 10 ≤ M ≤ 28. TABLE 6. CRYSTAL CHARACTERISTICS See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 7. AC CHARACTERISTICS, V

7 700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW CYCLE-TO-CYCLE JITTERPERIOD JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME PARAMETER MEASUREMENT INFORMATION

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

8 REVISION B 11/18/15

Table 8. Common SANs Application Frequencies Table 9. Confi guration Details for SANs Applications

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The 8432I-51 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA and V CCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic V CC pin and also shows that V CCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the V CCA pin. FIGURE 2. POWER SUPPLY FILTERING

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

10 REVISION B 11/18/15

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUTx and nFOUTx are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recom- mended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock com- ponent process variations. TERMINATION FOR LVPECL OUTPUTS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left fl oating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. REF_CLK I NPUT For applications not requiring the use of the test clock, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

FIGURE 6. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) and the inner edges of pad pattern for the leads to avoid any shorts. achieved when an array of vias is incorporated in the land pattern. Enhance Leadfame Base Package, Amkor Technology.

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

12 REVISION B 11/18/15

FIGURE 7A. SCHEMATIC OF RECOMMENDED LAYOUT LAYOUT GUIDELINE The schematic of the 8432I-51 layout example used in this layout guideline is shown in Figure 7A. The 8432I-51 recommended PCB board layout for this example is shown in Figure 7B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. S_DATA FOUTN VCCA 125 8432-51 nc VEE TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE MR S_CLOCK S_DATA S_LOAD VCCA nXTAL_SEL REF_CLK X_OU T VCO_SEL nP_LOAD X_IN C16 10u 125 XTAL_SEL S_CLOCK S_LOAD FOUT C14 0.1u VCC=3.3V C15 0.1u + C11 0.01u VCC VCC REF_IN VCC TL1 Zo = 50 Ohm TL2 Zo = 50 Ohm 8432I-51

13 700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 7B. PCB BOARD LAYOUT FOR 8432I-51 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have the same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

14 REVISION B 11/18/15

This section provides information on power dissipation and junction temperature for the 8432I-51. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8432I-51 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 145mA = 502.425mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.465V, with all outputs switching) = 502.425mW + 60mW = 562.425mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 10A. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) TABLE 10B. THERMAL RESISTANCE θJA FOR 32-PIN VFQFN, FORCED CONVECTION Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX– VOH_MAX ) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX– VOL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R L ] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX ))/R L ] * (VCCO_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/R L ] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX ))/R L ] * (VCCO_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

16 REVISION B 11/18/15

The transistor count for 8432I-51 is: 3743 TABLE 11A. θ JA VS. AIR FLOW TABLE FOR 32 LEAD LQFP TABLE 11B. θ JA VS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W

17 700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 12A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-026 JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBA MINIMUM NOMINAL MAXIMUM N 32 A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

18 REVISION B 11/18/15

PACKAGE OUTLINE - K SUFFIX 32 LEAD VFQFN TABLE 12B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-220 JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL Minimum Maximum N 32 A 0.80 1.0 A1 0 0.05 A3 0.25 Reference b 0.18 0.30 e 0.50 BASIC N D N E D 5.0 D2 1.25 3.25 E 5.0 E2 1.25 3.25 L 0.30 0.50 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 12B below.

TABLE 13. ORDERING INFORMATION

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8432I-51 DATA SHEET

20 REVISION B 11/18/15

Rev Table Page Description of Change Date B 1 Pin Assignment - corrected typo on pin 25 from XTAL_OUT to XTAL_IN. 5/13/08 B T13 General Description - deleted the HiperClocks logo. Ordering Information Table - per PCN# N1209-02 updated die revision ordering and marking from “B” to “C”. Corrected LQFP lead-free marking from ICS8432BI-51L to ICS8432CI51L. Updated footer part number from revision “B” to “C”. 10/8/12 B Deleted “_PCN” from fi le name. 11/6/12 B Updated data sheet format. 11/18/15

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