8432CK-51LF

ICS8432-51 IDT | Alldatasheet

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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8432-51 IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 1 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 GENERAL DESCRIPTION The ICS8432-51 is a general purpose, dual output Crystal-to- 3.3V Differential LVPECL High Frequency Synthesizer. The ICS8432-51 has a selectable REF_CLK or crystal input. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel inter- face to the configuration logic. The low phase noise character- istics of the ICS8432-51 make it an ideal clock source for Giga- bit Ethernet, Fibre Channel 1 and 2, and Infiniband applica- tions. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 12MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter: 3.5ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
• Replaces the ICS8432-01 OSC VCO_SEL XTAL_SEL REF_CLK XTAL1 XTAL2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL FOUT0 nFOUT0 FOUT1 nFOUT1 TEST CONFIGURATION INTERFACE LOGIC ÷ M PHASE DETECTOR MR 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_OUT REF_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR nc VEE VEE nFOUT0 FOUT0 VCCO nFOUT1 FOUT1 VCC TEST XTAL_IN nP_LOAD VCO_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS8432-51 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View

in Table 3B, Programmable VCO Frequency Function Table. Frequency Characteristics, Table 5, NOTE 1. requires no external components for setting the loop bandwidth. tor. The output of the oscillator is fed into the phase detector. buffers. The divider provides a 50% output duty cycle. and N1 is passed directly to the M divider and N output divider. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed.

TABLE 1. PIN DESCRIPTIONS

1 M5 Input Pullup

of nP_LOAD input. LVCMOS / LVTTL interface levels. Function Table. LVCMOS / LVTTL interface levels. 8, 16 V EE Power Negative supply pins. driven LOW in parallel mode. LVCMOS / LVTTL interface levels. 10 V CC Power Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL inter face levels. 13 V CCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interf ace levels.

17 MR Input Pulldown

effect loaded M, N, and T values. LVCMOS / LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register

on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_CLOCK. LVCMOS / LVTTL interface levels. 20 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. 21 V CCA Power Analog supply pin.

22 XTAL_SEL Input Pullup

Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 REF_CLK Input Pulldown Referenc clock input. LVCMOS / LVTTL interface levels . XT AL_IN Input Crystal oscillator interface. XTAL_IN is the input. N output divider value. LVCMOS / LVTTL interface levels. 27 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 4 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L  Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LHX XL  Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LHX X  LD ata Contents of the shift register are passed to the M divider and N output divider. LHX X  L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LHX XH  Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care  = Rising edge transition  = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 00 1 2 50 7 00 0 1 2 125 350 10 4 6 2.5 1 75 1 1 8 31.25 87.5 VCO Frequency (MHz) M Divide 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 250 1 0 000001010 275 1 1 000001011 650 26 0 0 0 0 1 1 0 1 0 675 2 7 000011011 700 2 8 000011100 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz.

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 5 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 2V CC + 0.3 V REF_CLK 2 V CC + 0.3 V VIL Input Low Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 -0.3 0.8 V REF_CLK -0.3 1.3 V IIH Input High Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, REF_CLK, S_DAT A, S_LOAD, nP_LOAD VCC = VIN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL V CC = VIN = 3.465V 5 µA IIL Input Low Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, REF_CLK, S_DAT A, S_LOAD, nP_LOAD VCC = 3.465V , VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V , VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 2.6 V VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50 Ω to VCCO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC –0.15 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 135 mA ICCA Analog Supply Current 15 mA ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 32 Lead LQFP 47.9°C/W (0 lfpm) 32 Lead VFQFN 41.07°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability.

figure "3.3V Output Load Test Circuit". TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C maximum frequency of 25MHz, valid values of M are 10  M  28. TABLE 6. CRYSTAL CHARACTERISTICS See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditio ns. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 7. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 7 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW SCOPE Qx nQx LVPECL VEE -1.3V± 0.165V tsk(o) nFOUTx FOUTx nFOUTy FOUTy CYCLE-TO-CYCLE JITTERPERIOD JITTER FOUTx ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1

1000 Cycles

(First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nFOUTx FOUTx nFOUTx OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tPW tPERIOD tPW tPERIOD odc = x 100% OUTPUT RISE/FALL TIME VEE VCC, VCCO VCCA PARAMETER MEASUREMENT INFORMATION 20% 80% 80% 20% tR tF VSWIN G FOUTx nFOUTx

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 10 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω FOUT FIN RTT = Z o 1 ((VOH + VOL ) / (VCC – 2)) – 2 3.3V 125Ω 125Ω 84Ω 84Ω Zo = 50Ω Zo = 50Ω FOUT FIN The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUTx and nFOUTx are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

FIGURE 6. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –S IDE VIEW (DRAWING NOT TO SCALE) the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. land pattern must be connected to ground through these vias. Electrically Enhance Leadfame Base Package, Amkor Technology.

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 13 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 7B. PCB BOARD LAYOUT FOR ICS8432-51 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have the same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C14 C16 C15 VIA PIN 1 VCCA TL1, TL21N are 50 Ohm traces and equal length C11 TL1 TL1N GND Close to the input pins of the receiver VCC TL1 TL1N

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 14 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8432-51. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8432-51 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 135mA = 467.8mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.465V, with all outputs switching) = 467.8mW + 60mW = 527.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). θ θθ θθJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 10A. THERMAL RESISTANCE θ θθ θθJA FOR 32-PIN LQFP, FORCED CONVECTION θ θθ θθJA by Velocity (Linear Feet per Minute) TABLE 10B. THERMAL RESISTANCE θ θθ θθJA FOR 32-PIN VFQFN, FORCED CONVECTION Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.

• For logic high, V OUT = V OH_MAX = V CCO_MAX – 0.9V CCO_MAX – V OH_MAX ) = 0.9V
• For logic low, V OUT = V OL_MAX = V CCO_MAX – 1.7V CCO_MAX – V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX – 2V))/R L ] * (V CCO_MAX – V OH_MAX ) = [(2V – (V CCO_MAX – V OH_MAX ))/R L ] * (V CCO_MAX – V OH_MAX ) = Pd_L = [(V OL_MAX – (V CCO_MAX – 2V))/R L ] * (V CCO_MAX – V OL_MAX ) = [(2V – (V CCO_MAX – V OL_MAX ))/R L ] * (V CCO_MAX – V OL_MAX ) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 16 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for ICS8432-51 is: 3743 TABLE 11A. θ JA VS. AIR FLOW TABLE FOR 32 LEAD LQFP TABLE 11B. θ JA VS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE θ θθ θθJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θ θθ θθJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 17 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 12A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-026 JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBA MINIMUM NOMINAL MAXIMUM N 32 A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75  0° -- 7° ccc -- -- 0.10

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 18 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - K SUFFIX 32 LEAD VFQFN TABLE 12B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-220 JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL Minimum Maximum N 32 A 0.80 1.0 A1 00 .05 A3 0.25 Reference b 0.18 0.30 e 0.50 BASIC ND 8 NE 8 D 5.0 D2 3.0 3.30 E 5.0 E2 3.0 3.30 L 0.30 0.50 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This draw- ing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. To p View Index Area D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singulation A 0. 08 C C Seating Plane E2 E2 L (N -1)x e (Re f.) (Ref.) N & N Even N e (Ref.) N & N Odd e (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Base N OR Anvil Singulation

TABLE 13. ORDERING INFORMATION

IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 20 ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date A 2 Corrected labels on the Parallel & Serial Load Operations diagram. 12/18/02 B T4A Revised MR pin description. Power Supply table - changed IDD to 155mA max. from 130mA max., changed IDDA to 20mA max. from 15mA max., and changed IDDO to 55mA max. from 45mA max. 2/13/03 B 9 Added LVDS Driver Termination Section. 3/12/03 C T3B T4A General Description & Features - changed VCO min. from 200MHz to 250MHz and replaced throughout the datasheet in: (Functional Description pg2, T3C Program. Output Divider Func. Table pg4, and T5 Input Freq Charac. T able pg6). - Features - changed min. Output Frequency Range from 25MHz to 31.25MHz. Pin Descriptions Table - revised XTAL1, XT AL2 pin description. Pin Characteristics T able - changed CIN 4pF max. to 4pF typical. Prog. VCO Freq. Func. Table - deleted 200 and 225 rows, does not apply. Power Supply DC Characteristics T able - deleted VDDO & IDDO rows, does not apply. AC Characteristics Table - change FOUT 25MHz min. to 31.25MHz min. 5/9/03 C T1 Pin Assignment - corrected XT AL pins. Pin 24 is labeled XTAL2 and pin 25 is labeled XTAL1. Revised Parallel & Serial Load Operations diagram. Pin Descriptions Table - corrected XTAL pins to correspond with the pin number. Changed XTAL1 to read input and XT AL2 to read output. Updated Figure 5A schematic to correspond the XTAL pins with the Pin Assignment. Crystal section, corrected pin 24 to read XT AL2 and pin 25 to read XT AL1. 5/28/03 C T13 Features Section - added Lead-Free bullet. Ordering Information - added Lead-Free part number. 4/8/05 D T4A Added 32 Lead VFQFN Package for Pin Assignment. Power Supply DC Characteristics T able - changed VCCA min. from 3.135V to VCC - 0.15V . Crystal Characteristics Table - added Drive Level. Added LVCMOS to XTAL Interface. Added Recommendations for Unused Input and Output Pins. Added VFQFN package throughout the datasheet. 4/13/06 E T4C T13 13 - 14 Changed naming convention of TEST_CLK to REF_CLK, (pin 24) XTAL2 to XTAL_OUT, and (pin 25) XTAL1 to XTAL_IN. Changed throughout the datasheet. LVPECL DC Characteristics Table - corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 4C. VFQFN marking. 4/10/07 F 1 Pin Assignment - corrected typo on pin 25 from XT AL_OUT to XTAL_IN. Added VFQFN EPAD Thermal Release Path section. 5/13/08 F T12B T13 General Description - deleted the HiperClocks logo. Ordering Information Table - per PCN# N1209-02 updated die revision ordering and marking from "B" to "C". Updated footer part number from revision "B" to "C". 11/13/12

700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Tech Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without noti ce. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in cus tomer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of I DT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used he rein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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