84329B RENESAS | Alldatasheet

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Technical content

Features

  • Fully integrated PLL, no external loop filter requirements
  • One differential 3.3V L VPECL output
  • Parallel resonant crystal oscillator interface
  • Output frequency range: 31.25MHz – 700MHz
  • VCO range: 250MHz – 700MHz
  • Parallel interface for programming counter and output dividers during power-up
  • Serial 3 wire interface
  • RMS period jitter: 5.5ps (maximum)
  • Cycle-to-cycle jitter: 35ps (maximum)
  • 3.3V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Lead-free (RoHS 6) packaging Block Diagram Pin Assignments FOUT nFOUT OSC XT AL_IN XT AL_OUT S_LOAD OE S_DA T A S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL TEST CONFIGURA TION INTERFACE LOGIC ÷1 6 PHASE DETECTOR ÷1 91 0 1 1 1 2 1 3 1 4 1 5 1 6 32 31 30 29 28 27 26 25 S_CLOCK S_DATA S_LOAD VCCA VCCA nc nc XTAL_IN nc XTAL_OUT OE nP_LOAD nc FOUT nFOUT VEE VCC VCC TEST VEE VCC 84329B 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View

Characteristics, T able 6, NOTE 1. by a divider prior to being sent to each of the L VPECL output buffers. The divider provides a 50% output duty cycle. diagram for each mode. In parallel mode the nP_LOAD input is LOW.

  1. The frequency out is defined as follows:

Figure 1. Parallel & Serial Load Operations

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Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See T able 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Input Pullup M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. VEE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. Single-ended LVPECL interface levels. nFOUT Output Differential output pair for the synthesizer. LVPECL interface levels. S_CLOCK. LVCMOS/LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS/LVTTL interface levels. CCA Power Analog supply pin. XT AL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

REVISION B 07/29/14 4 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Function Tables Table 3A. Parallel and Serial Mode Function Table NOTE: L = LOW H = HIGH X = Don’t care  = Rising edge transition  = Falling edge transition Table 3B. Programmable VCO Frequency Function Table NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. Table 3C. Programmable Output DividerFunction Table Inputs ConditionsnP_LOAD M N S_LOAD S_CLOCK S_DATA X X X X X X Reset. M and N bits are all set HIGH. L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST mode 000.  Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. HX X L  Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. HX X  L Data Contents of the shift register are passed to the M divider and N output divider. HX X  L Data M divider and N output divider values are latched. H X X L X X Parallel or serial input do not affect shift registers. VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 2 5 0 011111010 2 5 1 2 5 1 011111011 2 5 2 2 5 2 011111100 2 5 3 2 5 3 011111101 5 0 9 5 0 9 111111101 5 1 0 5 1 0 111111110 5 1 1 5 1 1 111111111 Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 1 250 700 0 1 2 125 350 1 0 4 62.5 175 1 1 8 31.25 87.5

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC =V CCA = 3.3V±5%, T A = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC =V CCA = 3.3V±5%, T A = 0°C to 70°C NOTE 1: Outputs terminated with 50  to VCC/2. See Parameter Measurement Information section. Load T est Circuit diagrams. Item Rating Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC+ 0.5V Outputs, I O Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 32-Lead LQFP 47.9 C/W (0 lfpm) Storage Temperature, T STG -65Ct o1 5 0 C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 125 mA ICCA Analog Supply Current 15 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current S_CLOCK, S_DATA, S_LOAD V CC =V IN = 3.465V 150 µA nP_LOAD, OE M0:M8, N0, N1 VCC =V IN = 3.465V 5 µA IIL Input Low Current S_CLOCK, S_DATA, S_LOAD VCC = 3.465V , VIN =0 V - 5 µ A nP_LOAD, OE M0:M8, N0, N1 VCC = 3.465V , VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 2.6 V VOL Output Low Voltage TEST; NOTE 1 0.5 V

NOTE 1: Outputs terminated with 50  to VCC –2 V . Table 5. Crystal Characteristics Table 6. Input Frequency Characteristics, VCC =V CCA = 3.3V±5%, T A = 0°C to 70°C valid values of M are 160  M  448. Table 7. AC Characteristics, VCC =V CCA = 3.3V±5%, T A = 0°C to 70°C See Parameter Measurement Information section. Characterized using 16MHz XT AL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications Section.

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

7 REVISION B 07/29/14

Parameter Measurement Information 3.3/3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Rise/Fall Time Period Jitter Output Duty Cycle/Pulse Width/Period Setup and Hold Time SCOPE Qx nQx VEE VCC, -1.3V±0.165V VCCA tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1

1000 Cycles

20% 80% 80% 20% tR tF VSWING VOH VREF VOL Mean Period (First edge after trigger) Reference Point (T rigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10 -7)% of all measurements Histogram nFOUT FOUT tHOLD tHOLD tSET -UP tSET -UP tSET -UP S_DA T A SL_CLOCK S_LOAD M0:M8 N0:N1 nP_LOAD

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

9 REVISION B 07/29/14

Overdriving the XTAL Interface The XT AL_IN input can be overdriven by an L VCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XT AL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V L VCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 4A shows an example of the interface diagram for a high speed 3.3V L VCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50  applications, R1 and R2 can be 100 . This can also be accomplished by removing R1 and changing R2 to 50 . The values of the resistors can be increased to reduce the loading for a slower and weaker L VCMOS driver. Figure 4B shows an example of the interface diagram for an L VPECL driver. This is a standard L VPECL termination with one side of the driver feeding the XT AL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

11 REVISION B 07/29/14

Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for L VPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output is a low impedance follower output that generate ECL/L VPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50  transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 6A. 3.3V LVPECL Output Termination Figure 6B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 o =5 0  o =5 0 LVPECL Input 3.3V 3.3V

This section provides information on power dissipation and junction temperature for the 84329B. Equations and example calculations are also provided. The total power dissipation for the 84329B is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 5% = 3.465V , which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature is 125°C. a multi-layer board, the appropriate value is 47.9°C/W per T able 8 below. board (single layer or multi-layer). Table 8. Thermal Resistance JA for 32-Lead LQFP , Forced Convection

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  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. L VPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 9. JA vs. Air Flow Table for a 32-Lead LQFP

15 REVISION B 07/29/14

Table 10. Package Dimensions for 32-Lead LQFP

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Ordering Information

Table 11. Ordering Information

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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Rev Table Page Description of Change Date A 1 Features Section - added “Parallel resonant” to crystal bullet. 12/15/04 B T11 Features Section - corrected Output frequency range from 25MHz to 31.25MHz. Added Lead-Free bullet. Updated Parallel & Serial Load Operations. Crystal Table - added Drive Level. Ordering Information Table - added Lead-Free part numbers and note. 6/10/05 B T11 Power Supply Filtering Techniques - added ferrite bead sentence. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added Lead-Free marking. 1/18/06 B 9 Added LVCMOS to XTAL Interface section. Updated format throughout the datasheet. 12/21/07 B AMR T9A T11 12-13 all Removed ICS from part number throughout. Features, last bullet: removed leaded option wording. Pin Assignment: deleted 28-Lead Pin Assignment. Removed 28-Lead PLCC from Package Thermal Impedance. Updated the ‘Overdriving the Crystal Interface’ note. Updated the ‘Termination for 3.3V LVPECL Outputs’ note. Deleted the Layout Guideline and Schematic section. Deleted Table 8A: Thermal Resistance  JA for 28-Lead PLCC, Forced Convection. Recalculated Tj using 32-Lead, 0lf/s: 47.9°C/W Deleted Table 9A:  JA vs. Air Flow Table for a 28-Lead PLCC. Deleted 28-Lead Package Outline. Deleted leaded option. Deleted Quantity from Tape and Reel. Updated Headers, Footers and Contact information. 7/28/14

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