ICS84329-01 IDT | Alldatasheet
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84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The ICS84329-01 is a general purpose, single output high frequency synthesizer. The VCO operates at a frequency range of 200MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of thecrystal frequency divided by 16. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as 125kHz to 1MHz can be achieved using a 16MHz crystal depending on the output dividers. ICS84329-01 28-Lead SOIC 7.5mm x 18.05mm x 2.25mm package body M Package Top View V EE TEST VCC nP_LOAD V CC XTAL2 XTAL1 nc nc V CCA S_LOAD S_DATA S_CLOCK V CC FOUT nFOUT V EE PIN A SSIGNMENTBLOCK DIAGRAM ICS84329-01 28-Lead PLCC 11.6mm x 11.4mm x 4.1mm V Package Top View 25 24 23 22 21 20 19 5 6 7 8 9 10 11 S_CLOCK S_DATA S_LOAD V CCA nc nc XTAL1 VEE TEST VCC VEE nFOUT FOUT VCC nP_LOAD Vcc XTAL2
FEATURES
- Fully integrated PLL, no external loop filter requirements
- 1 differential 3.3V LVPECL output
- Crystal oscillator interface
- Output frequency range: 25MHz to 700MHz
- VCO range: 200MHz to 700MHz
- Parallel interface for programming counter and output dividers during power-up
- Serial 3 wire interface
- RMS Period jitter: 5.5ps (maximum)
- Cycle-to-cycle jitter: 35ps (maximum)
- 3.3V supply voltage
- 0°C to 70°C ambient operating temperature
- Available in both standard (RoHS 5) and lead-free (RoHS 6) packages OSC XTAL1 XTAL2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL TEST CONFIGURATION INTERFACE LOGIC ÷ M ÷ 16 PHASE DETECTOR FOUT nFOUT
in the Input Frequency Characteristics, Table 6, NOTE 1. 16MHz crystal this provides a 1MHz reference frequency. of M (either too high or too low), the PLL will not achieve lock. vides a 50% output duty cycle.
16 MfVCO =
FIGURE 1. P ARALLEL & SERIAL LOAD OPERATIONS
TABLE 2. P IN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE stupnI snoitidnoC DAOL_PnM N D AOL_SK COLC_SA TAD_S XX X X X X . HGIHtesllaerastibNdnaM.teseR La taDa taDX X X dnaredividMotyltceriddessapstupniNdnaMnoataD .000edomTSET.redividtuptuoN ↑ ataDa taDL X X dedaolsniamerdnasretsigertupniotnidehctalsiataD .sruccotnevelairesalitnuronoitisnartWOLtxenlitnu HX XL ↑ ataD noatadhtiwdedaolsiretsigertfihS.edomtupnilaireS .KCOLC_SfoegdegnisirhcaenoATAD_S HX X ↑ La taD redividMehtotdessaperaretsigertfihsehtfostnetnoC .redividtuptuoNdna HX X ↓ La taD. dehctaleraseulavedividtuptuoNdnaedividM HX XL X X . sretsigertfihstceffatonodtupnilairesrolellaraP WOL=L:ETON HGIH=H eract'noD=X ↑ noitisnartegdegnisiR= ↓ noitisnartegdegnillaF= TABLE 3B. P ROGRAMMABLE VCO F REQUENCY FUNCTION TABLE ycneuqerFOCV )zHM( rediviDM 6528 214 62 36 18 4 2 1 8M7 M6 M5 M4 M3 M2 M1 M0 M 0020 02 011001000 1021 020 1 1 0 0 1 0 0 1 2022 02 0 1100 10 10 3023 02 011001011 9059 05 111111101 0150 15 111111110 1151 15 111111111 .zHM61foycneuqerflatsy rcaotdnopserrocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON TABLE 3C. P ROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE stupnI eulaVrediviDN )zHM(ycneuqerFtuptuO 1N0 Nm uminiMm umixaM 00 1 0 020 07 01 2 0 010 53 10 4 0 55 71 11 8 5 25 .78
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HO 1ETON;egatloVhgiHtuptuOV CC 4.1-V CC 9.0-V V LO 1ETON;egatloVwoLtuptuOV CC 0.2-V CC 7.1-V V GNIWS gniwSegatloVtuptuOkaeP-ot-kaeP 6.00 .1V 05htiwdetanimretstuptuO:1ETON Ω Vot CC .V2- TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI ,DAOL_Pn,DAOL_S ,KCOLC_S,ATAD_S 1N:0N,8M:0M 2V CC 3.0+V V LI egatloVwoLtupnI ,DAOL_Pn,DAOL_S ,KCOLC_S,ATAD_S 1N:0N,8M:0M 3.0-8 .0V I HI tnerruChgiHtupnI ,1N,0N,8M-0M DAOL_Pn V CC V= NI V564.3=5 A µ ,DAOL_S KCOLC_S,ATAD_S V CC V= NI V564.3=0 51A µ I LI tnerruCwoLtupnI ,1N,0N,8M-0M DAOL_Pn V CC V,V564.3= NI V0=0 51-A µ ,DAOL_S KCOLC_S,ATAD_S V CC V,V564.3= NI V0=5 -A µ V HO 1ETON;egatloVhgiHtuptuO 6.2V V LO 1ETON;egatloVwoLtuptuO 5.0V 05htiwdetanimretstuptuO:1ETON Ω Vot CC ehtni"tiucriCtseTdaoLtuptuOV3.3"erugifeeS.2/ .noitces"noitamrofnItnemerusaeMretemaraP" lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanA 531.33 .35 64.3V I EE tnerruCylppuSrewoP 011A m I ACC tnerruCylppuSgolanA 51A m ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, VO -0.5V to VCC + 0.5V Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C TABLE 5. C RYSTAL CHARACTERISTICS TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION PERIOD JITTER CYCLE-TO-CYCLE J ITTER3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx nQx LVPECL VEE ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD SETUP AND HOLD VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram -1.3V ± 0.165V nFOUT FOUT Clock Outputs 20% 80% 80% 20% tR tF VSWING tPW tPERIOD tPW tPERIOD odc = x 100% FOUT nFOUT OUTPUT RISE/FALL TIME tHOLD tHOLD tSET -UP tSET -UP tSET -UP S_DATA S_CLOCK S_LOAD M0:M8 N0:N1 nP_LOAD VCC, VCCA
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 6B. PCB BOARD LAYOUT FOR ICS84329-01 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND G ROUNDING Place the decoupling capacitors C1, C2 and C3, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
- The differential 50 Ω output traces should have the same length.
- Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
- Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
- To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
- Make sure no other signal traces are routed between the clock trace pair.
- The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. PIN 2 Signals Traces VIA C11
50 Ohm
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84329-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84329-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW
- Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 30mW = 411.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8A. T HERMAL RESISTANCE θθθθθJA FOR 28-PIN SOIC, FORCED CONVECTION TABLE 8B. T HERMAL RESISTANCE θθθθθJA FOR 28-PIN PLCC, FORCED CONVECTION θθθθθJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 60.8°C/W 53.2°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θθθθθJA by Velocity (Linear Feet per Minute) 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 7. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TRANSISTOR C OUNT The transistor count for ICS84329-01 is: 4408 TABLE 9A. θJAVS. AIR FLOW SOIC TABLE θθθθθJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 60.8°C/W 53.2°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θθθθθJA by Velocity (Linear Feet per Minute) TABLE 9B. θJAVS. AIR FLOW PLCC TABLE
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - M SUFFIX FOR 28 LEAD SOIC TABLE 10A. P ACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-013, MO-119 LOBMYS sretemilliM MUMINIMM UMIXAM N8 2 A- -5 6.2 1A0 1.0- - 2A5 0.25 5.2 B3 3.01 5.0 C8 1.02 3.0 D0 7.710 4.81 E0 4.70 6.7 eC ISAB72.1 H0 0.015 6.01 h5 2.05 7.0 L0 4.07 2.1 α °0° 8
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA LOBMYSM UMINIMM UMIXAM N 82 A 91.47 5.4 1A 92.25 0.3 2A 75.11 1.2 b 33.03 5.0 c 91.02 3.0 D 23.217 5.21 1D 34.118 5.11 2D 58.46 5.5 E 23.217 5.21 1E 34.118 5.11 2E 58.46 5.5 TABLE 10B. P ACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-018
TABLE 11. O RDERING INFORMATION the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TEEHSYROTSIHNOISIVER veRe lbaTe gaPe gnahCfonoitpircseDe taD B6 T6 -elbaTscitsiretcarahCycneuqerFtupnI .xaMzHM02ot.xaMzHM52morfLATXdetadpu 2dna1setoNedulcniotworLATXrehtonadedda .noitcesecafretnIrotallicsOdnatupnIlatsyrCdeddA 20/41/20 B1 T .margaidsnoitarepOdaoLlaireS&lellaraPdetadpU VdegnahC CC .snoitpircsedlatsyrcdna .tamrofdetadpU 20/81/21 C .sredividhtiwN÷decalper,margaiDkcolB ottimil.nimzHM02degnahcdna.xamzHM71ottimil.xamzHM02degnahC .2etoNdesiveR.nimzHM71 ycneuqerflatsyrcemasdedda,noitcesecafretnIrotallicsO&tupnIlatsyrC .eton 30/3/4 D C4T 11T 41-31 .tellubeerf-daeldedda-noitceSserutaeF .margaiDsnoitarepOdaoLlaireS&lellaraP,1erugiFdetcerroC .lacipytFp4ot.xamFp4morfNICdegnahc-scitsiretcarahCniP Vdetcerroc-elbaTscitsiretcarahCCDLCEPVL HO Vmorf.xam CC otV0.1- V CC .V9.0- Vtcelferotnoitapissidrewopdetcerroc-snoitaredisnoCrewoP HO elbaTnixam .C4 ,10-MA92348SCIrofrebmuntrapeerf-daeldedda-elbaTnoitamrofnIgniredrO deddA.10-VA92348SCIrofgnikramdnarebmuntrapeerf-daeldeddadna .etoneerf-dael 70/01/4 D 11T8 1 rebmuNredrO/traPmorfxiferpSCIdevomer-elbaTnoitamrofnIgniredrO .egakcapCIOSdael82rofgnikrameerf-daeldeddA.nmuloc .egaPtcatnoCdeddA .SCImorfTDIhtiwretoof/redaehs'teehsataddetadpU 01/7/8
84329AM-01 www.idt.com REV. D AUGUST 7, 2010 ICS84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com
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