84329-01

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84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84329-01 28-Lead SOIC 7.5mm x 18.05mm x 2.25mm package body M Package Top View V EE TEST VCC nP_LOAD V CC XTAL2 XTAL1 nc nc V CCA S_LOAD S_DA TA S_CLOCK V CC FOUT nFOUT VEE PIN A SSIGNMENT The 84329-01 is a general purpose, single output high frequency synthesizer. The VCO operates at a frequency range of 200MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the crystal frequency divided by 16. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as 125kHz to 1MHz can be achieved using a 16MHz crystal depending on the output dividers. BLOCK DIAGRAM

• Fully integrated PLL, no external loop filter requirements
• 1 differential 3.3V LVPECL output
• Crystal oscillator interface
• Output frequency range: 25MHz to 700MHz
• VCO range: 200MHz to 700MHz
• Parallel interface for programming counter and output dividers during power-up
• Serial 3 wire interface
• RMS Period jitter: 5.5ps (maximum)
• Cycle-to-cycle jitter: 35ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages OSC XTAL1 XTAL2 S_LOAD S_DA TA S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL TEST CONFIGURATION INTERFACE LOGIC ÷ M ÷ 16 PHASE DETECTOR FOUT nFOUT GEneral Description FEATURES

in the Input Frequency Characteristics, Table 6, NOTE 1. 16MHz crystal this provides a 1MHz reference frequenc y. of M (either too high or too low), the PLL w ill not achieve lock. vides a 50% output duty cycle.

16 MfVCO = fxtal x

FIGURE 1. P ARALLEL & SERIAL LOAD OPERATIONS

TABLE 2. P IN CHARACTERISTICS TABLE 1. P IN DESCRIPTIONS M4, M5, M6, M7, M8 Input Pullup M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pullup Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. VEE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. nFOUT, FOUT Output Differential output for the synthesizer. 3.3V LVPECL interface levels. on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS / LVTTL interface levels. VCCA Power Analog supply pin. XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. the M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions nP_LOAD M N S_LOAD S_CLOCK S_DATA X X X X X X Reset. M and N bits are all set HIGH. L Data Data X X X Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. HX XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. HX X ↑ LD a t a Contents of the shift register are passed to the M divider and N output divider. HX X ↓ L Data M divide and N output divide values are latched. H X X L X X Parallel or serial input do not affect shift registers. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. P ROGRAMMABLE VCO F REQUENCY FUNCTION TABLE VCO Frequency (MHz) M Divider 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 200 200 0 1 1 0 0 1 0 0 0 201 201 0 1 1 0 0 1 0 0 1 202 202 0 1 1 0 0 1 0 1 0 203 203 0 1 1 0 0 1 0 1 1 509 509 1 1 1 1 1 1 1 0 1 510 510 1 1 1 1 1 1 1 1 0 5 1 1 5 1 1 111111111 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. TABLE 3C. P ROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 1 200 700 0 1 2 100 350 10 4 5 0 1 7 5 1 1 8 25 87.5

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, T A = 0°C TO 70°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage S_LOAD, nP_LOAD, S_DATA, S_CLOCK, M0:M8, N0:N1 2V CC + 0.3 V VIL Input Low Voltage S_LOAD, nP_LOAD, S_DATA, S_CLOCK, M0:M8, N0:N1 -0.3 0.8 V I IH Input High Current M0-M8, N0, N1, nP_LOAD VCC = VIN = 3.465V 5 µA S_LOAD, S_DATA, S_CLOCK V CC = VIN = 3.465V 150 µA IIL Input Low Current M0-M8, N0, N1, nP_LOAD VCC = 3.465V, VIN = 0V -150 µA S_LOAD, S_DATA, S_CLOCK V CC = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 2.6 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCC/2. See figure "3.3V Output Load Test Circuit" in the "Parameter Measurement Information" section. Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 110 mA ICCA Analog Supply Current 15 mA ABSOLUTE M AXIMUM R ATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, VO -0.5V to VCC + 0.5V Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only . Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, T A = 0°C TO 70°C range of 200MHz or 700MHz. Using the minimum frequency of 10MHz valid values of M are 320 ≤ M ≤ 511. Using the maximum frequency of 25MHz valid values of M are 128 ≤ M ≤ 448. NOTE 2: For crystal frequencies greater than 17MHz, a series tuning capacitor is required for proper operation. For more information, please refer to the Application In formation, "Crystal Input and Oscillator Interface". TABLE 5. C RYSTAL C HARACTERISTICS TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C See Parameter Measurement Information section. Characterized using a 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: See Applications section.

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION PERIOD JITTER CYCLE-TO-CYCLE J ITTER3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD SETUP AND HOLD -1.3V ± 0.165V nFOUT FOUT FOUT nFOUT OUTPUT RISE/FALL TIME S_DATA S_CLOCK S_LOAD M0:M8 N0:N1 nP_LOAD VCC, VCCA

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 6B. PCB BOARD LAYOUT FOR 84329-01 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND G ROUNDING Place the decoupling capacitors C1, C2 and C3, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have the same length.  Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.  Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.  To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.  Make sure no other signal traces are routed between the clock trace pair.  The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XT AL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. PIN 2 Signals Traces VIA C11

50 Ohm

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 84329-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 84329-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW
• Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 30mW = 411.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8A. THERMAL RESISTANCE θJA FOR 28-PIN SOIC, F ORCED CONVECTION TABLE 8B. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, F ORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 02 00 5 00 Single-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 60.8°C/W 53.2°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θJA by Velocity (Linear Feet per Minute) 02 00 5 00 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 7. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for 84329-01 is: 4408 TABLE 9A. θJAVS. AIR FLOW SOIC TABLE θJA by Velocity (Linear Feet per Minute) 02 00 5 00 Single-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 60.8°C/W 53.2°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 02 00 5 00 Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θJA by Velocity (Linear Feet per Minute) TABLE 9B. θJAVS. AIR FLOW PLCC TABLE

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - M SUFFIX FOR 28 LEAD SOIC TABLE 10A. P ACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-013, MO-119 SYMBOL Millimeters MINIMUM MAXIMUM N2 8 A- - 2 .65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 17.70 18.40 E 7.40 7.60 e 1.27 BASIC H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8°

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM N 28 A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D 12.32 12.57 D1 11.43 11.58 D2 4.85 5.56 E 12.32 12.57 E1 11.43 11.58 E2 4.85 5.56 TABLE 10B. P ACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-018

TABLE 11. O RDERING INFORMATION NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

84329AM-01 www.idt.com REV. D APRIL 9, 2014 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date BT 6 6 Input Frequency Characteristics Table -

• updated XTAL from 25MHz Max. to 20MHz Max.  added another XTAL row to include Notes 1 and 2 Added Crystal Input and Oscillator Interface section. 02/14/02 BT 1 Updated Parallel & Serial Load Operations diagram. Changed V CC and crystal descriptions. Updated format. 12/18/02 C Block Diagram, replaced ÷N with dividers. Changed 20MHz max. limit to 17MHz max. and changed 20MHz min. limit to 17MHz min. Revised Note 2. Crystal Input & Oscillator Interface section, added same crystal frequency note. 4/3/03 D T4C T11 13 - 14 Features Section - added lead-free bullet. Corrected Figure 1, Parallel & Serial Load Operations Diagram. Pin Characteristics - changed CIN from 4pF max. to 4pF typical. L VPECL DC Characteristics T able -corrected V OH max. from V CC - 1.0V to VCC - 0.9V. Power Considerations - corrected power dissipation to reflect V OH max in T able 4C. and added lead-free part number and marking for ICS84329AV-01. Added lead-free note. 4/10/07 D T11 18 Ordering Information Table - removed ICS prefix from Part/Order Number column. Added lead-free marking for 28 lead SOIC package. Added Contact Page. Updated datasheet's header/footer with IDT from ICS. 8/7/10 D 1 Corrected typo: put space between 'the crystal' 8/21/12 D T11 Updated replacement part number Ordering Information Table - removed leaded devices 4/9/14

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