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FemtoClocks™ Crystal-to-3.3V LVPECL Frequency Synthesizer With Integrated Fanout Buffer 843256I DATASHEET 843256I REVISION A 5/29/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843256I is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for Fibre Channel and Gigabit Ethernet applications. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for SONET. The low phase noise characteristics of the 843256I make it an ideal clock for these demanding applications.

FEATURES

 Six 3.3V differential LVPECL output pairs  Output frequency range: 62.5MHz to 625MHz

  • Crystal input frequency range: 15.625MHz to 25.5MHz
  • RMS phase jitter at 156.25MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.41ps (typical) @ 3.3V
  • Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V  -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package BLOCK DIAGRAM 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.92mm body package G Package Top View SELECT FUNCTION TABLE Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0002 5 12 5 0 0 1 25 2 12.5 0 1 0 25 4 6.25 0112 5 5 5 1003 2 13 2 1013 2 21 6 1103 2 4 8 1113 2 8 4 PIN ASSIGNMENT

2 REVISION A 5/29/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 3, 4 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 5, 6 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 7, 8 nQ0, Q0 Output Differential output pair. LVPECL interface levels.

9 PLL_BYPASS Input Pullup

Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. 12 FB_SEL Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. OUT Input Crystal oscillator interface. XTAL_IN is the input. N_SEL1 Input Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 3. CRYSTAL FUNCTION TABLE

FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER 843256I DATA SHEET

4 REVISION A 5/29/15

Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 37°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = 3.3V±5%, V CCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V CC = 3.3V±5%, V CCO Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current FB_SEL V CC = V IN = 3.465V 150 µA PLL_BYPASS, N_SEL0, N_SEL1 V CC = V IN = 3.465V 5 µA I IL Input Low Current FB_SEL V CC = 3.465V, V IN = 0V -5 µA PLL_BYPASS, N_SEL0, N_SEL1 V CC = 3.465V, V IN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage Vcc – 0.12 3.3 3.465 V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 190 mA I CCA Analog Supply Current 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage Vcc – 0.12 3.3 3.465 V V CCO Output Supply Voltage 2.375 2.5 2.625 V I EE Power Supply Current 190 mA I CCA Analog Supply Current 12 mA

TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. See Parameter Measurement Information section. NOTE 1: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. For NOTES, please see Table 6A above.

FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER 843256I DATA SHEET

6 REVISION A 5/29/15

TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz

7 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER OUTPUT RISE/FALL TIME

FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER 843256I DATA SHEET

8 REVISION A 5/29/15

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843256I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA , and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be con- nected to each V CCA pin. FIGURE 1. POWER SUPPLY FILTERING protection. A 1kΩ resistor can be used. pair should either be left fl oating or terminated. FIGURE 2. CRYSTAL INPUt INTERFACE were chosen to minimize the ppm error.

FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER 843256I DATA SHEET

10 REVISION A 5/29/15

TERMINATION FOR 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat-ing 50Ω to V CC - 2V. For V CC = 2.5V, the V CC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE Zo = 50 Ohm VCCO=2.5V Zo = 50 Ohm 2.5V 2,5V LVPECL Driver FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE VCCO=2.5V Zo = 50 Ohm 2,5V LVPECL Driver Zo = 50 Ohm 2.5V FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 2.5V 2,5V LVPECL Driver 250 Zo = 50 Ohm Zo = 50 Ohm 62.5 2.5V 250 VCCO=2.5V

11 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843256I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843256I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 190mA = 658.35mW
  • Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power _MAX (3.465V, with all outputs switching) = 658;.35mW + 180mW = 838.35mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.838W * 37°C/W = 116°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). TABLE 7B. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, E-PAD FORCED CONVECTION θJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 37°C/W 31°C/W 30°C/W

12 REVISION A 5/29/15

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 8. θ

FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER 843256I DATA SHEET

14 REVISION A 5/29/15

PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP, E-PAD TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum Nominal Maximum N2 4 A -- 1.10 A1 0.05 0.15 A2 0.85 0.90 0.95 b 0.19 0.30 b1 0.19 0.22 0.25 c 0.09 0.20 c1 0.09 0.127 0.16 D 7.70 7.80 7.90 E 6.40 BASIC E1 4.30 4.40 4.50 e 0.65 BASIC L 0.50 0.60 0.70 P 5.0 P1 3.2 α 0° 8° aaa 0.076 bbb 0.10 Reference Document: JEDEC Publication 95, MO-153

TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER 843256I DATA SHEET

16 REVISION A 5/29/15

Rev Table Page Description of Change Date Updated data sheet format. 5/29/15

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