DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
Features
- Two differential LVPECL output pairs
- Using a 25MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
- Crystal oscillator interface
- VCO frequency: 490MHz – 680MHz
- RMS Phase Jitter @ 156.25MHz, (1.875MHz – 20MHz) using a 25MHz crystal: 0.47ps (typical)
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature
- Industrial temperature available upon request
- Available in lead-free (RoHS 6) package Block Diagram Pin Assignment OSC Phase Detector VCO 490MHz - 680MHz Feedback Divider 0 0 ÷1 0 1 ÷2 1 0 ÷3 1 1 ÷4 (default) 0 0 ÷2 0 1 ÷4 1 0 ÷5 1 1 ÷8 (default) 0 = ÷25 (default) 1 = ÷32 QA nQA QB nQB SELA[0:1] FB_SEL SELB[0:1] XTAL_IN XTAL_OUT Pullup Pulldown Pullup 9nQA QA VCCO_A SELB0 SELB1 VCCO_B QB nQB XTAL_IN XTAL_OUT VEE SELA1 SELA0 VCC VCCA FB_SEL 843252 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package 843252 Datasheet FemtoClock® Crystal-to- 3.3V LVPECL Frequency Synthesizer
843252 Datasheet
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQB, QB Output Bank B differential output pair. LVPECL interface levels. 3V CCO_B Power Output supply pin for QB, nQB outputs. SELB0 Input Pullup Division select pins for Bank B. LVCMOS/LVTTL interface levels. 6V CCO_A Power Output supply pin for QA, nQA outputs. 7, 8 QA, nQA Output Bank A differential output pair. LVPECL interface levels. the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels. 10 V CCA Power Analog supply pin. 11 V CC Power Core supply pin. SELA1 Input Pullup Division select pins for Bank A. LVCMOS/LVTTL interface levels. 14 V EE Power Negative supply pin. XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
3©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Table 3A. Bank A Frequency Table Inputs Feedback Divider Bank A Output Divider M/N Multiplication Factor QA, nQA Output Frequency (MHz) Crystal Frequency (MHz) FB_SEL SELA1 SELA0 25 0 0 0 25 1 25 625 25 0 0 1 25 2 12.5 312.5 20 0 0 1 25 2 12.5 250 22.5 0 1 0 25 3 8.333 187.5 25 0 1 1 25 4 6.25 156.25 24 0 1 1 25 4 6.25 150 20 0 1 1 25 4 6.25 125 19.44 1 0 0 32 1 32 622.08 19.44 1 0 1 32 2 16 311.04 15.625 1 0 1 32 2 16 250 18.75 1 1 0 32 3 10.667 200 19.44 1 1 1 32 4 8 155.52 18.75 1 1 1 32 4 8 150 15.625 1 1 1 32 4 8 125
4©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Table 3B. Bank B Frequency Table Table 3C. Output Bank A Configuration Select Function Table Table 3E. Feedback Divider Configuration Select Function Table Table 3D. Output Bank B Configuration Select Function Table Inputs Feedback Divider Bank B Output Divider M/N Multiplicatio n Factor QB, nQB Output Frequency (MHz) Crystal Frequency (MHz) FB_SEL SELB1 SELB0 25 0 0 0 25 2 12.5 312.5 20 0 0 0 25 2 12.5 250 25 0 0 1 25 4 6.25 156.25 24 0 0 1 25 4 6.25 150 20 0 0 1 25 4 6.25 125 25 0 1 0 25 5 5 125 25 0 1 1 25 8 3.125 78.125 24 0 1 1 25 8 3.125 75 20 0 1 1 25 8 3.125 62.5 19.44 1 0 0 32 2 16 311.04 15.625 1 0 0 32 2 16 250 19.44 1 0 1 32 4 8 155.52 18.75 1 0 1 32 4 8 150 15.625 1 0 1 32 4 8 125 15.625 1 1 0 32 5 6.4 100 19.44 1 1 1 32 8 4 77.76 18.75 1 1 1 32 8 4 75 15.625 1 1 1 32 8 4 62.5 Inputs Outputs SELA1 SELA0 QA, nQA 00 ÷ 1 01 ÷ 2 10 ÷ 3 1 1 ÷4 (default) Input FB_SEL Feedback Divide 0 ÷25 (default) 1÷ 3 2 Inputs Outputs SELB1 SELB0 QB, nQB 00 ÷ 2 01 ÷ 4 10 ÷ 5 1 1 ÷8 (default)
5©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 92.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.10 3.3 V CC V VCCO_A, VCCO_B Power Supply Voltage 3.135 3.3 3.465 V ICCA Analog Supply Current 10 mA IEE Power Supply Current 145 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current FB_SEL V CC = VIN = 3.465V 150 µA SELA[1:0], SELB[1:0] VCC = VIN = 3.465V 5 µA IIL Input Low Current FB_SEL V CC = 3.465V, VIN = 0V -5 µA SELA[1:0], SELB[1:0] VCC = 3.465V, VIN = 0V -150 µA
NOTE 1: Output termination with 50 to VCCO_A, _B – 2V. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. Table 6. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C has been reached under these conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots.
7©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Typical Phase Noise at 625MHz Typical Phase Noise at 156.25MHz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.36ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
8©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Skew Output Rise/Fall Time RMS Phase Jitter Output Duty Cycle/Pulse Width/Period VCC, -1.3V± 0.165V VCCA VCCO_A, VCCO_B nQx Qx nQy Qy nQA, nQB QA, QB Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQA, nQB QA, QB
9©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016
Application Information
Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter per- formance, power supply isolation is required. The 843252 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCA, VCCO_A, and VCCO_B should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. Figure 1. Power Supply Filtering were chosen to minimize the ppm error. Figure 2. Crystal Input Interface
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface recommended only as guidelines. to maximize operating frequency and minimize signal distortion. clock component process variations.
Figure 5. 843252 Schematic Example
This section provides information on power dissipation and junction temperature for the 843252. Equations and example calculations are also provided. The total power dissipation for the 843252 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for devices is 125°C. a multi-layer board, the appropriate value is 92.4°C/W per Table 7 below. Table 7. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 8. JA vs. Air Flow Table for a 16 Lead TSSOP
15©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016
Ordering Information
Table 10. Ordering Information
16©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Rev Table Page Description of Change Date B T10 “General Description” - deleted HiperClocks logo and reference text. Ordering Information Table - deleted Tape & Reel count. Deleted all HiperClocks references throughout the datasheet. Deleted ICS prefix from part number throughout the datasheet. Updated datasheet header/footer. 1/19/16
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com Tech Support email: clocks@idt.com