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Femtoclocks™ Crystal-to-3.3V LVPECL Frequency Synthesizer W/Integrated Fanout Buffer 843246I Data Sheet ©2015 Integrated Device Technology, Inc December 8, 20151 GENERAL DESCRIPTION The 843246I is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for Fibre Channel and Gigabit Ethernet applications and is a member of the family of High Performance Clock Solutions from IDT. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 26.5625MHz crystal for a Fibre Channel. The low phase noise characteristics of the 843246I make it an ideal clock for these demanding applications. BLOCK DIAGRAM
FEATURES
- Six LVPECL outputs
- Crystal oscillator interface
- VCO range: 490MHz to 680MHz
- Crystal input frequency range: 25MHz to 33.333MHz
- RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.41ps (typical)
- Full 3.3V or 3.3V core, 2.5V output supply mode Core/Output 3.3V/3.3V 3.3V/2.5V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package 843246I 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.9mm body package G Package Top View SELECT FUNCTION TABLE Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0002 0 2 1 0 0012 0 4 5 0102 0 5 4 0 1 1 20 8 2.5 1002 4 3 8 1012 4 4 6 1102 4 6 4 1112 41 2 2 PIN ASSIGNMENT
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 3, 4 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 5, 6 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 7, 8 nQ0, Q0 Output Differential output pair. LVPECL interface levels.
9 PLL_BYPASS Input Pullup
Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. 12 FB_SEL Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. OUT Input Crystal oscillator interface. XTAL_IN is the input. N_SEL1 Input Pullup Output frequency select pins. LVCMOS/LVTTL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. TYPICAL APPLICATION FREQUENCY FUNCTION TABLE
©2015 Integrated Device Technology, Inc December 8, 20154 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, V EE = 0V, TA = -40°C TO 85°C TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = 3.3V±5%, V CCO EE = 0V, TA = -40°C TO 85°C TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V CC = 3.3V±5%, V CCO = 2.5V±5%, V EE = 0V, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 37°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current FB_SEL V CC = V IN = 3.465V 150 µA PLL_BYPASS, N_SEL0, N_SEL1 V CC = V IN = 3.465V 5 µA I IL Input Low Current FB_SEL V CC = 3.465V, V IN = 0V -5 µA PLL_BYPASS, N_SEL0, N_SEL1 V CC = 3.465V, V IN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.10 3.3 V CC V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 180 mA I CCA Analog Supply Current 10 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.10 3.3 V CC V V CCO Output Supply Voltage 2.375 2.5 2.625 V I EE Power Supply Current 180 mA I CCA Analog Supply Current 10 mA
TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. See Parameter Measurement Information section. NOTE 1: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. See Parameter Measurement Information section. NOTE 1: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc December 8, 20156 TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Gb Ethernet Filter to raw data Raw Phase Noise Data Gb Ethernet Filter TYPICAL PHASE NOISE AT 312.5MHZ @ 3.3V OFFSET FREQUENCY (HZ) 312.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Phase Noise Result by adding Gb Ethernet Filter to raw data Raw Phase Noise Data Gb Ethernet Filter NOISE POWER dBc Hz
©2015 Integrated Device Technology, Inc December 8, 20157 PARAMETER MEASUREMENT INFORMATION 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTEROUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT approaches are shown in the LVPECL Termination Application Note.
24 VCCO
FIGURE 6. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE /Electrically Enhance Leadframe Base Package, Amkor Technology.
This section provides information on power dissipation and junction temperature for the 843246I. Equations and example calculations are also provided. The total power dissipation for the 843246I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 180mA = 623.7mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6* 30mW = 180mW Total Power _MAX (3.465V, with all outputs switching) = 623.7mW + 180mW = 803.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.804W * 37°C/W = 114.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, E-PAD FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 9. PACKAGE DIMENSIONS FOR 24 LEAD TSSOP, E-PAD
TABLE 8. θ
TABLE 10. ORDERING INFORMATION
©2015 Integrated Device Technology, Inc December 8, 201517 REVISION HISTORY SHEET Rev Table Page Description of Change Date A from Part/Order number and LF note below the table. Updated datasheet header and footer. 12/8/15
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2015 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters
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