843242 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: epieczon
- PDF pages: 19
Technical content
Features
- Two differential LVPECL output pairs
- Using a 31.25MHz or 26.041666MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
- Crystal oscillator interface
- RMS Phase Jitter @ 625MHz, (1.875MHz – 20MHz) using a 25MHz crystal: 0.4ps (typical)
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature
- Lead-free (RoHS 6) packaging 843242 16-pin, 4.4mm x 5.0mm TSSOP Package (173 mil) SELA0 SELA1 VEE XTAL_OUT XTAL_IN FB_SEL VCCA VCC SELB0 SELB1 VCCO_B QB nQB nQA QA VCCO_A Pin Assignment Block Diagram OSC Phase Detector VCO 625MHz Feedback Divider 0 0 ÷1 0 1 ÷2 1 0 ÷4 (default) 1 1 ÷5 0 0 ÷1 0 1 ÷2 1 0 ÷4 (default) 1 1 ÷5 0 = ÷20 (default) 1 = ÷24 QA nQA QB nQB SELA[1:0] FB_SEL SELB[1:0] XTAL_IN XTAL_OUT 0 = Pullup 1 = Pulldown 1 = Pullup 0 = Pulldown Pulldown 31.25MHz or 26.041666MHz
843242 DATA SHEET
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Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 nQB Output Differential clock outp uts. LVPECL interface levels. 2 QB Output Differential clock outp uts. LVPECL interface levels. 3V CCO_B Power Output supply pin for QB, nQB outputs. 4 SELB1 Input Pullup Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels. 5 SELB0 Input Pulldown Division select pins for Bank B. Default = Low. LVCMOS/LVTTL interface levels. 6V CCO_A Power Output supply pin for QA, nQA outputs. 7 QA Output Differential clock outp uts. LVPECL interface levels. 8 nQA Output Differential clock outp uts. LVPECL interface levels.
9 FB_SEL Input Pulldown
10 V CCA Power Analog supply pin. 11 V CC Power Core supply pin. 12 SELA0 Input Pullup Division select pin for Bank A. Default = High. LVCMOS/LVTTL interface levels. 13 SELA1 Input Pulldown Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels. 14 V EE Power Negative supply pin. 15 XTAL_OUT Input Crystal oscillator interface XT AL_IN is the input, XTAL_OUT is the output. 16 XTAL_IN Input Crystal oscillator interface XTAL _IN is the input, XTAL_OUT is the output.
REVISION 1 1/30/15 3 FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS Function Tables Table 3A. Bank A Frequency Table Table 3B. Bank B Frequency Table Table 3C. Output Bank Configuration Select Function Table Table 3D. Feedback Divider Configuration Select Function Table Inputs Feedback Divider Bank A Output Divider M/N Multiplication Factor QA, nQA Output Frequency (MHz) Crystal Frequency (MHz) SELA1 SELA0 FB_SEL 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Inputs Feedback Divider Bank B Output Divider M/N Multiplication Factor QB, nQB Output Frequency (MHz) Crystal Frequency (MHz) SELB1 SELB0 FB_SEL 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Inputs Outputs Inputs Outputs SELA1 SELA0 QA SELB1 SELB0 QB 00 ÷ 1 00 ÷ 1 0 1 ÷2 (default) 0 1 ÷2 10 ÷ 4 10 ÷ 4 ( d e f a u l t ) 11 ÷ 5 11 ÷ 5 Inputs FB_DIV Feedback Divide 0 ÷20 (default) 1÷ 2 4
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Junction Temperature, TJ 125C Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.15 3.3 V CC V VCCO_A, VCCO_B Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 158 mA ICCA Analog Supply Current 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current FB_SEL, SELA1, SELB0 V CC = VIN = 3.465V 150 µA SELA0, SELB1 VCC = VIN = 3.465V 5 µA IIL Input Low Current FB_SEL, SELA1, SELB0 VCC = 3.465V, VIN = 0V -5 µA SELA0, SELB1 VCC = 3.465V, VIN = 0V -150 µA
NOTE 1: Output termination with 50 to VCCO_A, _B – 2V. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. Table 6. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ±5%, VEE = 0V, TA = 0°C to 70°C has been reached under these conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS
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Typical Phase Noise at 625MHz Ethernet Filter Phase Noise Result by adding an Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.36ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz)
REVISION 1 1/30/15 7 FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Skew Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period VCC, -1.3V± 0.165V VCCA VCCO_A, VCCO_B nQx Qx nQy Qy nQA, nQB QA, QB nQA, nQB QA, QB
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS
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Application Information
Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS
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Figure 6 (next page) shows an example 843242 application schematic in which the device is operated at VCC = 3.3V. This example focuses on functional connections and is not configuration specific, particularly in the selection of 31.25MHz crystals instead of 26.041666MHz. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application. The 12pF parallel resonant Fox FX325BS 31.25MHz crystal is used with tuning capacitors C1 = 15pF and C2 = 21pF , which are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal tuning capacitors are required for proper operation. As an alternate choice, a CL= 18pF HC-49/U crystal is shown with the appropriate tuning capacitors. These values may also require a slight adjustment depending on the parasitic capacity of the layout. Crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board. Capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. Routing I 2C under the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. In fact, I2C transition times are short enough to capacitively couple into the crystal if they are routed close enough to the crystal traces. In layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the XTAL_IN and XTAL_OUT pins, traces to the crystal pads, the crystal pads and the tuning capacitors. Using a crystal on the top layer as an example, void all signal and power layers under the crystal connections between the top layer and the ground plane used by the 843242. Then calculate the parasitic capacity to the ground and determine if it is large enough to preclude tuning the oscillator. If the coupling is excessive, particularly if the first layer under the crystal is a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. The ground connection of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning cap ground to the ground plane as close to the 843242 as possible as shown in the schematic. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843242 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 10 V CCA resistor and the 0.1µF capacitors in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Pull up and pull down resistors to set configuration pins can all be placed on the PCB side opposite to the device side to free up device side area if necessary. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. For additional layout recommendations and guidelines, contact clocks@idt.com.
Figure 6. 843242 Schematic Example
4 SE LB05
12 SE LA1
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This section provides information on power dissipation and junction temperature for the 843242. Equations and example calculations are also provided. The total power dissipation for the 843242 is the sum of the core power plus the power dissipated due to the load. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 81.2°C/W per Table 7 below. Table 7. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. Figure 8. LVPECL Driver Circuit and Termination To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
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Table 8. JA vs. Air Flow Table for a 16-Lead TSSOP
REVISION 1 1/30/15 15 FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 9. Package Dimensions for 16-Lead TSSOP Reference Document: JEDEC Publication 95, MO-153 ccc C 0.08 C aaa C SID NX b2 bbb C A B A NX L2 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0° 8° aaa 0.10
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS
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Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an “G” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION 1 1/30/15 17 FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZERS Revision History Sheet Rev Table Page Description of Change Date
1 T10
Block Diagram - added output clock lables. Ordering Information table - added note. Deleted “ICS” prefix from part number throughout the datasheet. Updated datasheet header/footer. 1/30/15
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