84321AYILFT

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260MHz, Crystal-to-3.3V Differential LVPECL Clock Synthesizer 84321I DATA SHEET 84321I REVISION B 11/5/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 84321I is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency Synthesizer The 84321I has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the confi guration logic. The low phase noise characteristics of the 84321I make it an ideal clock source for Fibre Channel 1, Fibre Channel 2, 10 Gigabit Fibre Channel, Gigabit Ethernet and 10 Gigabit Ethernet applications. BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 103.3MHz to 260MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter: 3ps (typical)
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.5ps (typical) Phase noise: 155.52MHz Offset Noise Power
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package For functional replacement part use 8T49N241 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL2 TEST_CLK XTAL_SEL V CCA S_LOAD S_DATA S_CLOCK MR nc V EE VEE nFOUT0 FOUT0 V CCO nFOUT1 FOUT1 V CC TEST XTAL1 nP_LOAD VCO_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 84321I

2 REVISION B 11/5/15

Frequency Characteristics, Table 5, NOTE 1. quires no external components for setting the loop bandwidth. lator. The output of the oscillator is fed into the phase detector. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed.

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

1 M5 Input Pullup

of nP_LOAD input. LVCMOS / LVTTL interface levels. Function Table. LVCMOS / LVTTL interface levels. EE Power Negative supply pins.

9 TEST Output

Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. LVPECL interface levels.

17 MR Input Pulldown

and T values. LVCMOS / LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on

the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. CLOCK. LVCMOS/LVTTL interface levels. MOS / LVTTL interface levels. CCA Power Analog supply pin.

22 XTAL_SEL Input Pullup

Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. 24, 25 XTAL2, XTAL1 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. N output divider value. LVCMOS / LVTTL interface levels. 27 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84321I DATA SHEET

4 REVISION B 11/5/15

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LH X X H ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 6 2 5 2 5 000011001 6 5 0 2 6 000011010 6 7 5 2 7 000011011 7 7 5 3 1 000011111 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz. Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 3 206.7 260 0 1 4 155 195 1 0 5 124 156 1 1 6 103.3 130 Input Output Frequency (MHz)Crystal (MHz) M Divider Value N Divider Value 19.44 32 4 155.52 19.53125 32 4 156.25 25 25 4 156.25 25 25 5 125 25.50 25 3 212.50 25.50 25 4 159.375 25.50 25 6 106.25 38.88 16 4 155.52 TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE TABLE 3D. COMMONLY USED CONFIGURATION FUNCTION TABLE

5 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 CC + 0.3 V TEST_CLK 2 V CC + 0.3 V VIL Input Low Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 -0.3 0.8 V TEST_CLK -0.3 1.3 V I IH Input High Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = VIN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL V CC = VIN = 3.465V 5 µA IIL Input Low Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 2.6 V V OL Output Low Voltage TEST; NOTE 1 0.5 V Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 180 mA ICCA Analog Supply Current 30 mA NOTE 1: Outputs terminated with 50Ω to VCCO/2. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to VCC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

6 REVISION B 11/5/15

“3.3V Output Load Test Circuit”. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C the 620MHz to 780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 ≤ M ≤ 55. Using the maximum frequency of 40MHz, valid values of M are 16 ≤ M ≤ 19. TABLE 6. CRYSTAL CHARACTERISTICS TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.

7 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE 25MHz Input RMS Phase Noise Jitter 12kHz to 20MHz = 3.0ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) PHASE NOISE (dBc)HZ 156.25MHz 125MHz 25.5MHz Input RMS Phase Noise Jitter 12kHz to 20MHz = 3.0ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) PHASE NOISE (dBc)HZ 106.25MHz 212.5MHz

260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84321I DATA SHEET

8 REVISION B 11/5/15

PARAMETER MEASUREMENT INFORMATION PERIOD JITTER OUTPUT SKEW3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME OUPUT DUTY CYCLE/PULSE WIDTH/PERIOD

10 REVISION B 11/5/15

the stack up of the P .C. board. FIGURE 4. POWER SUPPLY FILTERING

11 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 5B. PCB BOARD LAYOUT FOR 84321I The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have the same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL1) and 24 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.

12 REVISION B 11/5/15

This section provides information on power dissipation and junction temperature for the 84321I. Equations and example calculations are also provided. The total power dissipation for the 84321I is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW
• Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 623.7W + 60mW = 683.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

14 REVISION B 11/5/15

TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 10. PACKAGE DIMENSIONS

16 REVISION B 11/5/15

TABLE 11. ORDERING INFORMATION NOTE: Parts that are ordered with an “”LF”” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

17 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date B T11 12 - 13 Features Section, added lead-free bullet. Updated Figure 1, Parallel & Serial Load Operations Diagram. LVPECL DC Characteristics Table -corrected V OH max. from VCCO - 1.0V to VCCO - 0.9V. Power Considerations - corrected power dissipation to refl ect V OH max in Table 4C. Ordering Information Table - added lead-free part number, marking and note. 4/10/07 B T11 16 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/7/10 B T11 Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05. Ordering Information - removed leaded devices. 11/5/15

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