84320I-01

84320I-01 RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
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780MHz, Crystal-to-3.3V Differential LVPECL Frequency Synthesizer 84320I-01 DATASHEET 84320I-01 REVISION C DECEMBER 17, 2014 1 ©2014 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 84320I-01 is a general purpose, dual output Crystal-to-3.3V Differential LVPECLHigh Frequency Synthesizer. The 84320I-01 has a selectable TEST_CLK or crystal inputs. The VCOoperates at a frequency range of 620MHz to 780MHz. The VCO frequency is pro- grammed in steps equal to thevalue of the input reference or crystal frequency. The VCO and output frequency can be programmed using theserial or parallel interfaces to the confi guration logic. The low phase noise characteristics of the 84320I-01make it an ideal clock source for 10 Gigabit Ethernet, SONET, and Serial Attached SCSI applications. BLOCK DIAGRAM

FEATURES

• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 77.5MHz to 780MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
• Parallel or serial interface for programming counter and output dividers
• Duty cycle: 44% - 56% (N > 1)
• RMS period jitter: 2.0ps (typical)
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.38ps (typical)
• RMS phase noise at 155.52MHz (typical) Offset Noise Power
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_OUT TEST_CLK XTAL_SEL V CCA S_LOAD S_DATA S_CLOCK MR nc V EE VEE nFOUT0 FOUT0 V CCO nFOUT1 FOUT1 V CC TEST XTAL_IN nP_LOAD VCO_SEL 84320I-01 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View PIN ASSIGNMENT

2 REVISION C 12/17/14

Frequency Characteristics, Table 5, NOTE 1. requires no external components for setting the loop bandwidth. lator. The output of the oscillator is fed into the phase detector. and N1 is passed directly to the M divider and N output divider. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed.

TABLE 1. PIN DESCRIPTIONS

1 M5 Input Pullup

input. LVCMOS / LVTTL interface levels. Table. LVCMOS / LVTTL interface levels. 8, 16 V EE Power Negative supply pins.

9 TEST Output

Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. LVPECL interface levels. 13 V CCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. LVPECL interface levels.

17 MR Input Pulldown

loaded M, N, and T values. LVCMOS / LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on

the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. CLOCK. LVCMOS/LVTTL interface levels. MOS / LVTTL interface levels. CCA Power Analog supply pin.

22 XTAL_SEL Input Pullup

Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. N output divider value. LVCMOS / LVTTL interface levels. 27 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84320I-01 DATA SHEET

4 REVISION C 12/17/14

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LH X X H ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 1 620 780 0 1 2 310 390 1 0 4 155 195 1 1 8 77.5 97.5 VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 6 2 5 2 5 000011001 7 0 0 2 8 000011100 7 7 5 3 1 000011111 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz.

5 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 CC + 0.3 V TEST_CLK 2 V CC + 0.3 V VIL Input Low Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 -0.3 0.8 V TEST_CLK -0.3 1.3 V I IH Input High Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = VIN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL V CC = VIN = 3.465V 5 µA IIL Input Low Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 2.6 V VOL Output Low Voltage TEST; NOTE 1 0.5 V Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 155 mA ICCA Analog Supply Current 22 mA NOTE 1: Outputs terminated with 50Ω to VCCO/2. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, V O (LVCMOS) -0.5V to V CCO + 0.5V Outputs, I O (LVPECL) Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

6 REVISION C 12/17/14

“3.3V Output Load Test Circuit”. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C mum frequency of 40MHz, valid values of M are 16 ≤ M ≤ 19. TABLE 6. CRYSTAL CHARACTERISTICS

TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.

780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84320I-01 DATA SHEET

8 REVISION C 12/17/14

TYPICAL PHASE NOISE AT 155.52MHZ TYPICAL PHASE NOISE AT 622.08MHZ OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -19010 100 1k 10k 100k 1M 10M 100M 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 2.38ps (typical) Phase Noise Result by adding Sonet Bandpass Filter to raw data Raw Phase Noise Data OC-48 Sonet Bandpass Filter OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 622.08MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 2.48ps (typical) Phase Noise Result by adding Sonet Bandpass Filter to raw data Raw Phase Noise Data OC-48 Sonet Bandpass Filter 10 100 1k 10k 100k 1M 10M 100M

9 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION PERIOD JITTER OUTPUT SKEW3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIMERMS PHASE JITTER

780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84320I-01 DATA SHEET

10 REVISION C 12/17/14

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 84320I-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24 Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be connected to each V CCA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 2. POWER SUPPLY FILTERING tied from XTAL_IN to ground. 1kΩ resistor can be tied from the TEST_CLK to ground. protection. A 1kΩ resistor can be used. that there is no trace attached. output pair should either be left fl oating or terminated.

11 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS CRYSTAL INPUT INTERFACE A crystal can be characterized for either series or parallel mode operation. The 84320I-01 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with Figure 3. CRYSTAL INPUt INTERFACE accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3.

780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84320I-01 DATA SHEET

12 REVISION C 12/17/14

The schematic of the 84320I-01 layout example used in this layout guideline is shown in Figure 5A. The 84320I-01 recom- mended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The LAYOUT GUIDELINE FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT layout in the actual system will depend on the selected compo- nent types, the density of the components, the density of the traces, and the stack up of the P .C. board. S_LOAD 125 C16 10u 125 VCC=3.3V FOUT VCC S_CLOCK TL1 + VCCA VCC S_DATA VCC VCC C14 0.1u Zo = 50 Ohm nTL1 C11 0.01u Zo = 50 Ohm XTAL_SEL C15 0.1u FOUTN ICS84320i-01 nc VEE TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE MR S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL T_CLK X_OU T VCO_SEL nP_LOAD X_IN REF_IN

13 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FIGURE 5B. PCB BOARD LAYOUT FOR 84320I-01 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have the same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL_IN) and 24 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. TL1, TL21N are 50 Ohm traces and equal length VIA TL1N GND C15 TL1 R1 TL1 VCC C11 PIN 1 C14 TL1N C16 Close to the input pins of the receiver VCCA

14 REVISION C 12/17/14

This section provides information on power dissipation and junction temperature for the 84320I-01. Equations and example calculations are also provided. The total power dissipation for the 84320I-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.08mW
• Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 537.08mW + 60mW = 597.08mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

16 REVISION C 12/17/14

TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 10. PACKAGE DIMENSIONS

18 REVISION C 12/17/14

TABLE 11. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

19 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date B T11 18 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/4/10

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