ICS843207-350 IDT | Alldatasheet
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER ICS843207-350 IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 1 ICS843207CY-350 REV. A DECEMBER 3, 2007 Phase Detector VCO 620 - 750MHz ÷50 ÷95 ÷105 OSC Predivider
00 HiZ
01 ÷2 10 ÷8 11 ÷4 01 ÷2 10 ÷8 11 ÷4 01 ÷2 10 ÷8 11 ÷4 01 ÷2 10 ÷8 11 ÷4 01 ÷2 10 ÷8 11 ÷4 01 ÷2 10 ÷8 11 ÷4 01 ÷2 10 ÷8 11 ÷4 nQ0 SEL[1:0] nQ1 SEL[3:2] nQ2 SEL[5:4] nQ3 SEL[7:6] nQ4 SEL[9:8] nQ5 SEL[11:10] nQ6 SEL[13:12] Pulldown Pulldown Pulldown Pulldown Pulldown nPLL_SEL XTAL_IN XTAL_OUT REF_CLK nXTAL_SEL MODE MARGIN MR Pulldown 14MHz Pullup Pullup Pullup Pullup Pullup Pullup Pullup To O/P Dividers GENERAL DESCRIPTION The ICS843207-350 is a low phase-noise frequency margining synthesizer that targets clocking for high performance interfaces such as SPI4.2 and is a member of the HiPerClockS™ family of high performance clock solutions from IDT. In the default mode, each output can be configured individually to generate an 87.5MHz, 175MHZ or 350MHz LVPECL output clock signal from a 14MHz crystal input. There is also a frequency margining mode available where the device can be configured, using control pins, to vary the output frequency up or down from nominal by 5%. The ICS843207-350 is provided in a 48-pin LQFP package.
FEATURES
Seven independently configurable LVPECL outputs at 87.5MHz, 175MHz or 350MHz Individual high impedance control of each output Selectable crystal oscillator interface designed for 14MHz, 18pF parallel resonant crystal or LVCMOS single-ended input Output frequency can be varied ± 5% from nominal VCO range: 620MHz - 750MHz Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS BLOCK DIAGRAM VCCA VCC VCCO nQ6 V EE VCCO nQ5 nQ4 V CCO 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 VCCO nQ0 nQ1 VEE VCCO nQ2 nQ3 VCCO SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 SEL8 SEL9 SEL10 SEL11 SEL12 SEL13 ICS843207-350 48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View SEL1 SEL0 nPLL_SEL VCC XTAL_IN XTAL_OUT nXTAL_SEL REF_CLK V EE MR MARGIN MODE PIN ASSIGNMENT
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 2 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY FUNCTIONAL DESCRIPTION The ICS843207-350 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 14MHz fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining mode, the 14MHz crystal frequency is divided by 2 and a 7MHz reference frequency is applied to the phase detector. The VCO of the PLL operates over a range of 620MHz to 750MHz. The output of the M divider is also applied to the phase detector. The default mode for the ICS843207-350 is a nominal VCO frequency of 700MHz with each output configurable to divide by 2, 4 or 8. The nominal output frequency can be changed by placing the device into the margining mode using the mode pin and using the margin pin to change the M feedback divider. Frequency margining mode operation occurs when the MODE input is HIGH. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. The output of the VCO is scaled by an output divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the crystal input frequency, the M divider, the VCO frequency and the output frequency is provided in Table 1A. When changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration described above. TABLE 1A. FREQUENCY SELECT FUNCTION TABLE TABLE 1B. FREQUENCY MARGIN FUNCTION TABLE )zHM(LATXx LES1 -xLES) zHM(OCVr ediviDtuptuO) zHM(ycneuqerFtuptuO 410 0 0 07A /NZ iH 410 1 0 072 0 53 411 0 0 078 5 .78 411 10 074 5 71 EDOMN IGRAM) zHM(LATX) P(rediviD-erPr ediviDkcabdeeF) zHM(OCVe gnahC% 10 4 12 5 95 660 .5- 0X 4 11 0 50 07e doM.moN 11 4 12 5 015 370 .5+
TABLE 2. PIN DESCRIPTIONS TABLE 3. PIN CHARACTERISTICS
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 4 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VCCO = VEE = OV, TA = 0°C TO 70°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 65.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanAV CC 31.0–3 .3V CC V V OCC egatloVylppuStuptuO 531.33 .35 64.3V I EE tnerruCylppuSrewoP 012A m I ACC tnerruCylppuSgolanA 31A m TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = OV, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnIV CC V3.3=2 V CC 3.0+V V LI egatloVwoLtupnIV CC V3.3=3 .0-8 .0V I HI tupnI tnerruChgiH ,NIGRAM,KLC_FER ,LES_LLPn,EDOM LES_LATXn,RM V CC V= NI 564.3=0 51A µ ]31:0[LESV CC V= NI 564.3=5 A µ I LI tupnI tnerruCwoL ,NIGRAM,KLC_FER ,LES_LLPn,EDOM LES_LATXn,RM V CC ,V564.3= V NI V0= 5-A µ ]31:0[LES V CC ,V564.3= V NI V0= 051-A µ Δ /t Δv noitisnarTtupnI etaRllaF/esiR EDOM,]31:0[LES 02V /sn
TABLE 6. CRYSTAL CHARACTERISTICS TABLE 7. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = OV, TA = 0°C TO 70°C
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 6 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 350MHZ 350MHz RMS Phase Noise Jitter 12kHz to 20MHz = 1.54ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 175MHZ 175MHz RMS Phase Noise Jitter 12kHz to 20MHz = 1.48ps (typical) Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
10 Gigabit Ethernet Filter
Phase Noise Result by adding
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 7 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY PARAMETER MEASUREMENT INFORMATION tPW tPERIOD tPW tPERIOD odc = x 100% Q0:Q6 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME Clock Outputs 20% 80% 80% 20% tR tF VSWING nQ0:nQ6 Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPE Qx nQx LVPECL VEE -1.3V ± 0.165V VCC, VCCO VCCA
protection. A 1k Ω resistor can be used. pair should either be left floating or terminated. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE and R2 in parallel should equal the transmission line impedance. also be accomplished by removing R1 and making R2 50 Ω.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER 10 ICS843207CY-350 REV. A DECEMBER 3, 2007 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUT VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω FOUT FIN RTT = Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V 125Ω 125Ω 84Ω 84Ω Zo = 50Ω Zo = 50Ω FOUT FIN The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, ter- minating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION designed to drive 50 Ω transmission lines. Matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
This section provides information on power dissipation and junction temperature for the ICS843207-350. Equations and example calculations are also provided. The total power dissipation for the ICS843207-350 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 210mA = 727.65mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 7 * 30mW = 210mW Total Power _MAX (3.63V , with all outputs switching) = 727.65mW + 210mW = 937.65mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming air flow at 1 meter per second and a multi-layer board, the appropriate value is 55.9°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). θθθθθJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W
TABLE 8. THERMAL RESISTANCE θθθθθJA FOR 48-PIN LQFP, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 9. θ
TABLE 10. PACKAGE DIMENSIONS
TABLE 11. ORDERING INFORMATION
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Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 ICS843207-350 FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER PRELIMINARY © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA