843204I-01

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Crystal-to-3.3V LVPECL Frequency Synthesizer 843204I-01 DATA SHEET 843204I-01 REVISION A 11/5/15 1 ©2015 Integrated Device Technology, Inc. PLLOSC ÷4 OSC 25MHz 19.44MHz PLL ÷4 622.08MHz 155.52MHz 625MHz 156.25MHz OEA0 SELA0 OEA1 SELA1 OEB0 SELB0 OEB1 SELB0 QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 nPLL_BYPASS_A IN_SELA CLK0 XTAL_IN0 XTAL_OUT0 IN_SELB CLK1 nCLK1 XTAL_IN1 XTAL_OUT1 Pullup nPLL_BYPASS_B Pullup Pullup Pullup Pulldown Pullup/pulldown Pulldown GENERAL DESCRIPTION The 843204I-01 is a 4 output LVPECL Synthe-sizer optimized to generate Gigabit Ethernet and SONET reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal, 155.52MHz and 156.25MHz frequencies can be generated. The 843204I-01 uses IDT’s FemtoClock TM low phase noise VCO technology and can achieve 1ps or lower typical RMS phase jitter.

FEATURES

 Four 3.3V LVPECL outputs Selectable crystal oscillator interface or clock inputs  Supports the following output frequencies: 155.52MHz and 156.25MHz  VCO range: 560MHz - 680MHz  RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 13MHz): 0.6ps (typical)  RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.7ps (typical)  Full 3.3V supply mode  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) package  For functional replacement part us 8T49N285 PIN ASSIGNMENTBLOCK DIAGRAM 843204I-01

48 Lead TSSOP

6.1mm x 12.5mm x 0.925mm package body G Package Top View nQA1 QA1 nQA0 QA0 nc VCCO_A SELA1 SELA0 nPLL_BYPASS_A nc nc nc nc XTAL_IN1 XTAL_OUT1 CLK1 nCLK1 IN_SELB V CCO_B nc QB0 nQB0 QB1 nQB1 IN_SELA CLK0 XTAL_IN0 XTAL_OUT0 nc V EE OEA0 OEA1 V CC VCCA nPLL_BYPASS_B nc SELB0 V EE OEB0 OEB1 V CC SELB1 V CCA nc nc nc nc nc

2 REVISION A 11/5/15

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 1, 2 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 3, 4 nQA0, QA0 Output Differential output pair. LVPECL interface levels. Power Output supply pin for Bank A outputs. selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. 9 nPLL_BYPASS_A Input Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active. 16 CLK1 Input Pulldown Non-inverting differential clock input. /2 bias voltage when left fl oating. nCLK1 inputs. LVCMOS/LVTTL interface levels. Power Output supply pin for Bank B outputs. 21, 22 QB0, nQB0 Ouput Differential output pair. LVPECL interface levels. 23, 24 QB1, nQB1 Ouput Differential output pair. LVPECL interface levels. selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels. 33 OEB1 Input Pullup Output enable pin. QB1/nQB1 outputs are enable. LVCMOS/LVTTL interface levels. 34 OEB0 Input Pullup Output enable pin. QB0/nQB0 outputs are enabled. LVCMOS/LVTTL interface levels. selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels. 38 nPLL_BYPASS_B Input Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active. 41 OEA1 Input Pullup Output enable pin. QA1/nQA1 outpus are enabled. LVCMOS/LVTTL interface levels. 42 OEA0 Input Pullup Output enable pin. QA0/nQA0 outputs are enabled. LVCMOS/LVTTL interface levels. 47 CLK0 Input Pulldown LVCMOS/LVTTL clock input. input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO_A = V CCO_B = 3.3V±10%, V EE = 0V, TA = -40°C TO 85°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCO_A = V CCO_B = 3.3V±10%, V EE = 0V, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 54.8°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 2.97 3.3 3.63 V V CCA Analog Supply Voltage V CC – 0.22 3.3 V CC V V CCO_A, V CCO_B Output Supply Voltage 2.97 3.3 3.63 V I EE Power Supply Current 165 mA I CCA Analog Supply Current 22 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current CLK0, SELA0, SELA1 V CC = V IN = 3.63V 150 µA nPLL_BYPASS_A, nPLL_BYPASS_B, IN_ SELA, IN_SELB, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 V CC = V IN = 3.63V 5 µA I IL Input Low Current CLK0, SELA0, SELA1 V CC = 3.63V, V IN = 0V -5 µA nPLL_BYPASS_A, nPLL_BYPASS_B, IN_ SELA, IN_SELB, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 V CC = 3.63V, V IN = 0V -150 µA

4 REVISION A 11/5/15

TABLE 5. AC CHARACTERISTICS, V TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE 1: Defi ned as skew within a bank of outputs at the same supply voltags and with equal load conditions. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: See Phase Noise plot.

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3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER DIFFERENTIAL INPUT LEVEL3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT BANK SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME

FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET

6 REVISION A 11/5/15

The 843204I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below FIGURE 2. CRYSTAL INPUt INTERFACE were chosen to minimize the ppm error.

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843204I-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA , and V CCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each V CCA POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING

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FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER 843204I-01 DATA SHEET

8 REVISION A 11/5/15

TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left fl oating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. CLK I NPUT For applications not requiring the use of a clock input, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

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This section provides information on power dissipation and junction temperature for the 843204I-01. Equations and example calculations are also provided. The total power dissipation for the 843204I-01 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = V CC_MAX * I EE_MAX = 3.63V * 165mA = 598.95mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power _MAX (3.63V, with all outputs switching) = 598.95mW + 120mW = 718.95mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = J unction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assumig no air fl ow and a multi-layer board, the appropriate value is 54.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θJA FOR 48-PIN TSSOP, FORCED CONVECTION

10 REVISION A 11/5/15

1. Calculations and Equations.

pose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

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TABLE 7. θ TABLE 8. PACKAGE DIMENSIONS

12 REVISION A 11/5/15

TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

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3.3V LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date AT 9 Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05. Ordering Information - Removed leaded devices and ICS from orderable part number. Updated data sheet format. 11/5/15

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