ICS843204I IDT | Alldatasheet
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FEMTOCLOCK™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER ICS843204I IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 1 ICS843204AGI REV. A MARCH 18, 2009 PLLOSC ÷4 OSC 25MHz 19.44MHz PLL ÷4 622.08MHz 155.52MHz 625MHz 156.25MHz OEA0 SELA0 OEA1 SELA1 OEB0 SELB0 OEB1 SELB0 QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 nPLL_BYPASS_A IN_SELA CLK0 XTAL_IN0 XTAL_OUT0 nPLL_BYPASS_B IN_SELB CLK1 XTAL_IN1 XTAL_OUT1 Pullup Pullup Pullup Pullup Pulldown Pulldown GENERAL DESCRIPTION The ICS843204I is a 4 output LVPECL Synthesizer optimized to generate Gigabit Ethernet and SONET reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal, 155.52MHz and 156.25MHz frequencies can be generated. The ICS843204I uses IDT’s FemtoClock TM low phase noise VCO technology and can achieve 1ps or lower typical RMS phase jitter. The ICS843204I is pack- aged in a 48-pin TSSOP package.
FEATURES
Four 3.3V LVPECL outputs Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Supports the following output frequencies: 155.52MHz and 156.25MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 20MHz): 0.98ps (typical) RMS phase jitter @ 156.25MHz, using a 19.44MHz crystal (1.875MHz - 20MHz): 0.52ps (typical) Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS PIN ASSIGNMENT ICS843204I
48 Lead TSSOP
6.1mm x 12.5mm x 0.925mm package body G Package Top View nQA1 QA1 nQA0 QA0 nc VCCO_A SELA1 SELA0 nPLL_BYPASS_A nc nc nc nc XTAL_IN1 XT AL_OUT1 CLK1 IN_SEL_B nPLL_BYPASS_B V CCO_B nc QB0 nQB0 QB1 nQB1 IN_SEL_A CLK0 XTAL_IN0 XTAL_OUT0 nc V EE OEA0 OEA1 VCC VCCA_A nc nc SELB0 VEE OEB0 OEB1 V CC SELB1 V CCA_B nc nc nc nc nc BLOCK DIAGRAM
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 3 ICS843204AGI REV. A MARCH 18, 2009 ICS843204I FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 54.8°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC7 9.23 .33 6.3V V A_ACC + V B_ACC egatloVylppuSgolanAV CC 22.0–3 .3V CC V V ,A_OCC V B_OCC egatloVylppuStuptuO7 9.23 .33 6.3V I EE tnerruCylppuSrewoP 071A m I CC tnerruCylppuSeroC 521A m I A_ACC I+ B_ACC tnerruCylppuSgolanA 22A m I A_OCC I+ B_OCC tnerruCylppuStuptuO 32A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 2V CC 3.0+V V LI tupnI egatloVwoL 3.0-8 .0V I HI tupnI tnerruChgiH ,1KLC,0KLC 1ALES,0ALES V CC V= NI V36.3=0 51A µ ,A_SSAPYB_LLPn ,B_SSAPYB_LLPn ,B_LES_NI,A_LES_NI ,0BEO,0BLES,1BLES 1AEO,0AEO,1BEO V CC V= NI V36.3=5 A µ I LI tupnI tnerruCwoL ,1KLC,0KLC 1ALES,0ALES V CC V,V36.3= NI V0=5 -A µ ,A_SSAPYB_LLPn ,B_SSAPYB_LLPn ,B_LES_NI,A_LES_NI ,0BEO,0BLES,1BLES 1AEO,0AEO,1BEO V CC V,V36.3= NI V0=0 51-A µ
TABLE 5. AC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±10%, VEE = 0V, TA = -40°C TO 85°C TABLE 4. CRYSTAL CHARACTERISTICS
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 5 ICS843204AGI REV. A MARCH 18, 2009 ICS843204I FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical) TYPICAL PHASE NOISE AT 156.25MHZ TYPICAL PHASE NOISE AT 155.52MHZ 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.98ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWERdBc Hz NOISE POWER Phase Noise Result by adding a SONET Filter to raw data Raw Phase Noise Data SONET Jitter Filter Phase Noise Result by adding a Gigabit Ethernet Filter to raw data Raw Phase Noise Data Gigabit Ethernet Jitter Filter OFFSET FREQUENCY (HZ)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 6 ICS843204AGI REV. A MARCH 18, 2009 ICS843204I FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION tPW tPERIOD tPW tPERIOD odc = x 100% QA0, QA1 QB0, QB1 RMS PHASE JITTER BANK SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME 20% 80% 80% 20% tR tF VSWING nQA0, nQA1 nQB0, nQB1 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD t sk(b) Qy Qx nQy nQx Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPE Qx nQxLVPECL VEE -1.3V ± 0.33V VCC, VCCO_A, VCCO_B VCCA_A QA0, QA1 QB0, QB1 nQA0, nQA1 nQB0, nQB1 Where X = A or B outputs V CCA_B
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 7 ICS843204AGI REV. A MARCH 18, 2009 ICS843204I FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS843204I pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCA_A, VCCA_B, VCCO_A and VCCO_B should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V CC pin and also shows that V CCA requires that an additional10 Ω resistor along with a 10µF bypass capacitor be connected to the V CCA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING 1kΩ resistor can be tied from the CLK input to ground. protection. A 1k Ω resistor can be used. pair should either be left floating or terminated.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 9 ICS843204AGI REV. A MARCH 18, 2009 ICS843204I FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR 3.3V LVPECL OUTPUTS VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω FOUT FIN RTT = Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V 125Ω 125Ω 84Ω 84Ω Zo = 50Ω Zo = 50Ω FOUT FIN The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, ter- minating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION designed to drive 50 Ω transmission lines. Matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
This section provides information on power dissipation and junction temperature for the ICS843204I. Equations and example calculations are also provided. The total power dissipation for the ICS843204I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.63V * 170mA = 617.10mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power _MAX (3.63V , with all outputs switching) = 617.10mW + 120mW = 737.10mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 51°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.737W * 51°C/W = 122.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 48-PIN TSSOP, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 7. θ
TABLE 8. PACKAGE DIMENSIONS
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 15 ICS843204AGI REV. A MARCH 18, 2009 ICS843204I FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TEEHSYROTSIHNOISIVER veRe lbaTe gaPe gnahCfonoitpircseDe taD A9 T .Fp72ot2C/qCdegnahc,2erugiF,ecafretnItupnIlatsyrC rebmunredro/trapmorfxiferp"SCI"deteled-elbaTnoitamrofnIgniredrO .nmuloc 90/81/3
FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.
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San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA