843202I RENESAS | Alldatasheet
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- Manufacturer or author: rdvorak
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Technical content
680MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer 843202I DATA SHEET 843202I REVISION A 5/26/16 1 ©2016 Integrated Device Technology, Inc. PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 GENERAL DESCRIPTION The 843202I is a 2 output LVPECL Synthesizer optimized to generate Gigabit Ethernet and SONET reference clock frequencies and is a member of the family of high performance clock solutions from IDT. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal, 155.52MHz and 156.25MHz frequencies can be generated. The part also allows the use of a recovered clock at QB output. The 843202I uses IDT’s FemtoClock TM low phase noise VCO technology and can achieve 1ps or lower typical RMS phase jitter. The 843202I is packaged in a 32-pin LQFP package.
FEATURES
Two 3.3V LVPECL outputs Selectable crystal oscillator interface or one differential recov- ered clock inputs Supports the following output frequencies: 155.52MHz and 156.25MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz – 1.3MHz): 0.86ps (typical) RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz –- 20MHz): 0.56ps (typical) Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package For functional replacement part use 8T49N242 SELBX FUNCTION TABLE Control Inputs Outputs SEL[1:0] nQB, QB
00 High, Low
01 REC_CLK
10 156.25MHz driven by XTAL_0 11 155.52MHz driven by XTAL_1 PIN ASSIGNMENT 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 OEA V CC VCCA SEL0 V EE OEB V CC SEL1 VCCO_A nc XTAL_IN1 XTAL_OUT1 nc REC_CLK nREC_CLK VCCO_B VCCA nc nc nc nc nQB QB nc V EE nc XTAL_OUT0 XTAL_IN0 nc nQA QA nc 843202I 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View BLOCK DIAGRAM VCO 625MHz ÷25 25MHz OSC 156.25MHz Phase Detector VCO 622.08MHz ÷32 19.44MHz OSC 155.52MHz Phase Detector QA nQA QB nQB Pullup Pulldown Pullup Pullup Pullup OEA XTAL_IN0 XTAL_OUT0 XTAL_IN1 XTAL_OUT1 REC_CLK nREC_CLK SEL[1:0] OEB
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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS Power Output supply pin for Bank A output. 6 REC_CLK Input Pulldown Non-inverting differential recovered clock inputs. 7 nREC_CLK Input Pullup Inverting differential recovered clock inputs. Power Output supply pin for Bank B output. 10, 11 QB, nQB Ouput Differential output pair. LVPECL interface levels. 17, 21 SEL1, SEL0 Input Pullup Select pins. See SELx Function Table. LVCMOS/LVTTL interface levels. 19 OEB Input Pullup Output enable pin. QB/nQB output is enabled. LVCMOS/LVTTL interface levels. 24 OEA Input Pullup Output enable pin. QA/nQA output is enabled. LVCMOS/LVTTL interface levels. 30, 31 nQA, QA Output Differential output pair. LVPECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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680MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO_A = V CCO_B TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCO_A = V CCO_B ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 80.8°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 2.97 3.3 3.63 V V CCA Analog Supply Voltage V CC – 0.22 3.3 V CC V V CCO_A, V CCO_B Output Supply Voltage 2.97 3.3 3.63 V I EE Power Supply Current 138 mA I CCA Analog Supply Current 22 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current OEA, OEB, SEL0, SEL1 VCC = VIN = 3.63V 5µ A I IL Input Low Current OEA, OEB, SEL0, SEL1 VCC = 3.63V, VIN = 0V -150 µA TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, V CC = V CCO_A = V CCO_B Symbol Parameter Test Conditions Minimum Typical Maximum Units I IH Input High Current REC_CLK V CC = V IN = 3.465V 150 µA nREC_CLK V CC = V IN = 3.465V 5 µA I IL Input Low Current REC_CLK V CC = 3.63V, V IN = 0V -5 µA nREC_CLK V CC = 3.63V, V IN = 0V -150 µA V PP Peak-to-Peak Input Voltage 0.15 1.3 V V CMR Common Mode Input Voltage; NOTE 1 V EE + 0.5 V CC – 0.85 V NOTE 1: Common mode voltage is defi ned as V IH
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TABLE 5. AC CHARACTERISTICS, V TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. All parameters measured up to 170MHz unless otherwise specifi ed. NOTE 1: See Phase Noise plots.
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680MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 155.52MHZ 155.52MHz RMS Phase Jitter (Random) 12kHz to 1.3MHz = 0.86ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M Filter Phase Noise Result by adding a Filter to raw data Raw Phase Noise Data dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 156.25MHZ OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M Filter Phase Noise Result by adding a Filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.56ps (typical) dBc Hz NOISE POWER
680MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 843202I DATA SHEET
6 REVISION A 5/26/16
PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME
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680MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE The 843202I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below FIGURE 2. CRYSTAL INPUt INTERFACE
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APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843202I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA , and V CCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each V CCA POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING were chosen to minimize the ppm error.
8 REVISION A 5/26/16
resistance is not required but can be added for additional protection. pair should either be left fl oating or terminated. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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680MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS
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TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION This section provides information on power dissipation and junction temperature for the 843202I. Equations and example calculations are also provided. The total power dissipation for the 843202I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.63V * 138mA = 500.9mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.63V, with all outputs switching) = 500.9mW + 60mW = 560.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 71.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
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- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
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TABLE 7. θ
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TABLE 8. PACKAGE DIMENSIONS
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TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
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680MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date Updated data sheet format. 10/15/15 A Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 5/26/16
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