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Frequency Margining Synthesizer 843201-375 DATASHEET 843201-375 REVISION A 8/21/15 1 ©2015 Integrated Device Technology, Inc. Q nQ VCCO VCC VEE MR nPLL_SEL nc VCC MODE nc XTAL_IN XTAL_OUT MARGIN VEE nc GENERAL DESCRIPTION The 843201-3 75 is a low phase-noise frequency margining synthesizer. In the default mode, the device nominally generates a 375MHz LVPECL output clock signal from a 25MHz crystal input. There is also a frequency margining mode available where the device can be confi gured, using control pins, to vary the output frequency up or down from nominal by 5%. The 8 43201-375 is provided in a 16-pin TSSOP package.

FEATURES

  • One 375MHz nominal L VPECL output
  • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant cr ystal
  • Output frequency can be varied ± 5% from nominal VCO range: 700MHz - 800MHz
  • RMS phase jitter @ 375MHz, using a 25MHz crystal (12kHz - 20MHz): 0.72ps (typical) @ 3.3V
  • Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • Functional replacement part 8T49N241-dddNLGI BLOCK DIAGRAM PIN ASSIGNMENT 843201-375 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View Phase Detector VCO 700 - 800MHz ÷30 (÷57, ÷63) OSC Predivider ÷2 ÷2 Q nQ Pulldown 25MHz Pulldown Pulldown Pulldown nPLL_SEL XTAL_IN XTAL_OUT MODE MARGIN MR

2 REVISION A 8/21/15

requires no external components for setting the loop bandwidth. return to the default nominal confi guration described above. TABLE 1. FREQUENCY MARGIN FUNCTION TABLE

3 FEMTOCLOCK® CRYSTAL-TO-LVPECL

TABLE 2. PIN DESCRIPTIONS TABLE 3. PIN CHARACTERISTICS TABLE 4. MODE CONTROL INPUT FUNCTION TABLE

0 Default Mode

1 Frequency Margining Mode

2 MODE Input Pulldown MODE pin. LOW = default mode. HIGH = frequency margining mode. LVCMOS/LVTTL interface levels. 3, 8, 9 nc Unused No connect. 6 Margin Input Pulldown Sets the frequency margin to ±5% in frequency margining mode. See Table 1. LVCMOS/LVTTL interface levels. the output dividers. When LOW, PLL is enabled. LVCMOS/LVTTL interface levels.

11 MR Input Pulldown

abled. LVCMOS/LVTTL interface levels. 15, 16 nQ, Q Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

FEMTOCLOCK® CRYSTAL-TO-LVPECL 375MHZ, FREQUENCY MARGINING SYNTHESIZER 843201-375 DATA SHEET

4 REVISION A 8/21/15

TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, TA = 0°C TO 70°C ABSOLUTE MAXIMUM RATINGS Supply V oltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 99.9°C/W (0 lfpm) Stor age Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Positive Supply Voltage 3.135 3.33 .465 V V CCO Output Supply Voltage 3.135 3.33 .465 V I EE Power Supply Current 108 mA I CC Power Supply Current 96m A I CCO Output Supply Current 12 mA TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, V CC = 3.3V±5%,V CCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Positive Supply Voltage 3.135 3.33 .465 V V CCO Output Supply Voltage 2.375 2.5 2.625 V I EE Power Supply Current 108 mA I CC Power Supply Current 96m A I CCO Output Supply Current 12 mA TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Positive Supply Voltage 2.375 2.5 2.625 V V CCO Output Supply Voltage 2.375 2.5 2.625 V I EE Power Supply Current 101 mA I CC Power Supply Current 95m A I CCO Output Supply Current 6m A

5 FEMTOCLOCK® CRYSTAL-TO-LVPECL

TABLE 6. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE: It is not recommended to overdrive the crystal input with an external clock.

FEMTOCLOCK® CRYSTAL-TO-LVPECL 375MHZ, FREQUENCY MARGINING SYNTHESIZER 843201-375 DATA SHEET

6 REVISION A 8/21/15

TABLE 7A. AC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, TA = 0°C TO 70°C TABLE 7B. AC CHARACTERISTICS, V CC = 3.3V±5%,V CCO = 2.5V±5%, TA = 0°C TO 70°C TABLE 7C. AC CHARACTERISTICS, V CC = V CCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 375 MHz tjit(F) RMS Phase Jitter (Random); NOTE 1 375MHz, Integration Range: 12kHz - 20MHz 0.72 ps t R / t F Output Rise/Fall Time 20% to 80% 200 550 ps odc Output Duty Cycle 4 9 51 % NOTE 1: Refer to Phase Noise Plot. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 375 MHz tjit(F) RMS Phase Jitter (Random); NOTE 1 375MHz, Integration Range: 12kHz - 20MHz 0.72 ps t R / t F Output Rise/Fall Time 20% to 80% 200 550 ps odc Output Duty Cycle 4 9 51 % NOTE 1: Refer to Phase Noise Plot. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 375 MHz tjit(F) RMS Phase Jitter (Random); NOTE 1 375MHz, Integration Range: 12kHz - 20MHz 0.88 ps t R / t F Output Rise/Fall Time 20% to 80% 200 550 ps odc Output Duty Cycle 4 9 51 % NOTE 1: Refer to Phase Noise Plot.

7 FEMTOCLOCK® CRYSTAL-TO-LVPECL

375MHZ, FREQUENCY MARGINING SYNTHESIZER SONET Filter Raw Phase Noise Data Phase Noise Result by adding a SONET Filter to raw data SONET Filter Raw Phase Noise Data Phase Noise Result by adding a SONET Filter to raw data OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 375MHZ @ 3.3V/2.5V 375MHz RMS Phase Noise Jitter 12kHz to 20MHz = 0.72ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 375MHZ @ 3.3V/3.3V 375MHz RMS Phase Noise Jitter 12kHz to 20MHz = 0.72ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k 100k 1M 10M 100M

FEMTOCLOCK® CRYSTAL-TO-LVPECL 375MHZ, FREQUENCY MARGINING SYNTHESIZER 843201-375 DATA SHEET

8 REVISION A 8/21/15

Phase Noise Result by adding a SONET Filter to raw data OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 375MHZ @ 2.5V/2.5V 375MHz RMS Phase Noise Jitter 12kHz to 20MHz = 0.88ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k 100k 1M 10M 100M

9 FEMTOCLOCK® CRYSTAL-TO-LVPECL

375MHZ, FREQUENCY MARGINING SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME

FEMTOCLOCK® CRYSTAL-TO-LVPECL 375MHZ, FREQUENCY MARGINING SYNTHESIZER 843201-375 DATA SHEET

10 REVISION A 8/21/15

APPLICATION INFORMATION

The 843201- 375 has been characterized with 1 8pF parallel resonant crystals. The capacitor values shown in FIGURE 1. CRYSTAL INPUt INTERFACE resonant crystal and were chosen to minimize the ppm error. resistance is not required but can be added for additional protection.

11 FEMTOCLOCK® CRYSTAL-TO-LVPECL

375MHZ, FREQUENCY MARGINING SYNTHESIZER TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recom- mended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock com- ponent process variations.

FEMTOCLOCK® CRYSTAL-TO-LVPECL 375MHZ, FREQUENCY MARGINING SYNTHESIZER 843201-375 DATA SHEET

12 REVISION A 8/21/15

TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 Ω to V CC - 2V. For V CC = 2.5V, the V CC - 2V is very close to ground level. The R 3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLEFIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 Zo = 50 Ohm 250 2.5V 2,5V LVPECL Driver 62.5 250 Zo = 50 Ohm 2.5V VCC=2.5V Zo = 50 Ohm Zo = 50 Ohm 2,5V LVPECL Driver VCC=2.5V 2.5V 2,5V LVPECL Driver VCC=2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm

13 FEMTOCLOCK® CRYSTAL-TO-LVPECL

This section provides information on power dissipation and junction temperature for the 843201-375. Equations and example calculations are also provided. The total power dissipation for the 843201-375 is the sum of the core power plus the power dissipated due to loading. = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 108mA = 374.2mW
  • Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.465V) = 374.2mW + 30mW = 404.2mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air fl ow and a multi-layer board, the appropriate value is 99.9°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.404W * 99.9°C/W = 110°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (multi-layer). θJA by Velocity (Linear Feet per Minute)

TABLE 8. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION

14 REVISION A 8/21/15

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.

  • For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX ) = 0.9V
  • For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R L ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX ))/R L ] * (VCCO_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R L ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX ))/R L ] * (VCCO_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION

15 FEMTOCLOCK® CRYSTAL-TO-LVPECL

TABLE 9. θ

16 REVISION A 8/21/15

TABLE 10. PACKAGE DIMENSIONS

17 FEMTOCLOCK® CRYSTAL-TO-LVPECL

TABLE 11. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

FEMTOCLOCK® CRYSTAL-TO-LVPECL 375MHZ, FREQUENCY MARGINING SYNTHESIZER 843201-375 DATA SHEET

18 REVISION A 8/21/15

Rev Table Page Description of Change Date AT 6 Deleted HiPerClockS references. Crystal Characteristics Table - added note. Deleted application note, LVCMOS to XTAL Interface. Deleted quantity from tape and reel. 4/26/13 Updated data sheet format. 5/27/15 A Product Discontinuation Notice - Last time buy expires August 14, 2016 PDN CQ-15-04 8/21/15

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