84314AYLF

84314 IDT | Alldatasheet

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350MHz, Crystal-to-3.3V/2.5V LVPECL Frequency Synthesizer W/Fanout Buffer 84314 Data Sheet ©2016 Integrated Device Technology, Inc Revision C January 8, 20161 GENERAL DESCRIPTION The 84314 is a general purpose quad output frequency synthesizer and a member of the family of High Performance Clock Solutions from IDT. When the device uses parallel loading, the M bits are programmable and the output divider is hard-wired for divide by 2 thus providing a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output divider can be set for either divide by 2 or divide by 4, providing a frequency range of 62.5MHz to 350MHz. The low cycle-cycle jitter and broad frequency range of the 84314 make it an ideal clock generator for a variety of demanding applications which require high performance. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• Fully integrated PLL
• 4 differential 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS TEST_CLK input
• Output frequency range: 62.5MHz to 350MHz
• VCO range: 250MHz to 700MHz
• Parallel interface for programming counter and output dividers during power-up
• Serial 3 wire interface
• Cycle-to-cycle jitter: 23ps (typical)
• Output skew: 16ps (typical)
• Output duty cycle: 49% < odc < 51%, fout ≤ 125MHz
• Full 3.3V or mixed 3.3V core, 2.5V operating supply
• 0°C to 85°C ambient operating temperature
• Lead-Free package available 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View

84314 Data Sheet

during power-up. In parallel mode, the N output divider is set to 2. In serial mode, the N output divider can be set for either ÷2 or ÷4. in Table 3B, Programmable VCO Frequency Function Table. M divider and N output divider on each rising edge of S_CLOCK. Input Frequency Characteristics, Table 5, NOTE 1. output of the M divider is also applied to the phase detector. modes are parallel and serial. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. **NOTE: “N” can only be controlled through serial loading. TABLE 1. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)

TABLE 2. PIN DESCRIPTIONS 6V EE Power Negative supply pin. 7V CC Power Core power supply pin. 8, 17 V CCO Power Output supply pins. 9, 10 Q0, nQ0 Output Differential output for the synthesizer. LVPECL interface levels. 11, 12 Q1, nQ1 Output Differential output for the synthesizer. LVPECL interface levels. 13, 14 Q2, nQ2 Output Differential output for the synthesizer. LVPECL interface levels. 15, 16 Q3, nQ3 Output Differential output for the synthesizer. LVPECL interface levels.

18 MR Input Pulldown

M values. LVCMOS / LVTTL interface levels.

19 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register

on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. of S_CLOCK. LVCMOS / LVTTL interface levels. MOS / LVTTL interface levels. 22 V CCA Power Analog supply pin.

23 XTAL_SEL Input Pullup

when LOW. LVCMOS / LVTTL interface levels. 24 TEST_CLK Input Pulldown Test clock input. LVCMOS interface levels. 25, 26 XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. is loaded into the M divider. LVCMOS / LVTTL interface levels. 28 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 3. PIN CHARACTERISTICS

©2016 Integrated Device Technology, Inc Revision C January 8, 20164 TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE VCO Frequency (MHz) M Divide 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 250 1 25 0 0 1111101 252 1 26 0 0 1111110 254 1 27 0 0 1111111 256 1 28 0 1 0000000 696 3 48 1 0 1011100 698 3 49 1 0 1011101 700 3 50 1 0 1011110 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 16MHz. Inputs Conditions MR nP_LOAD M S_LOAD S_CLOCK S_DATA H X X X X X Reset. Forces outputs LOW. L L Data X X X Data on M inputs passed directly to the M divider. L ↑ Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X L ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X ↓ L Data M divider and N output divider values are latched. L H X L X X Parallel or serial input do not affect shift registers. LH X H ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition Input Output Frequency (MHz) N Logic N Divide Qx, nQx Minimum Maximum 0 2 125 350 1 4 62.5 175 TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)

©2016 Integrated Device Technology, Inc Revision C January 8, 20165 TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage TEST_CLK; NOTE 1 2.35 V CC + 0.3 V VCO_SEL, XTAL_SEL, nP_LOAD, MR, M0:M8, S_ LOAD, S_DATA, S_CLOCK 2V CC + 0.3 V VIL Input Low Voltage TEST_CLK; NOTE 1 -0.3 0.95 V VCO_SEL, XTAL_SEL, nP_LOAD, MR, M0:M8, S_ LOAD, S_DATA, S_CLOCK -0.3 0.8 V IIH Input High Current M0:M7, MR, nP_LOAD, S_ CLOCK, S_DATA, S_LOAD VCC = VIN = 3.465V 150 µA M8, XTAL_SEL, VCO_SEL V CC = VIN = 3.465V 5 µA TEST_CLK V CC = VIN = 3.465V 200 µA IIL Input Low Current M0:M7, MR, nP_LOAD, S_ CLOCK, S_DATA, S_LOAD VCC = 3.465V, VIN = 0V -5 µA M8, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA NOTE:1 Characterized with 1ns input edge rate. Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IEE Power Supply Current 150 mA ICCA Analog Supply Current 17 mA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to VCC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466. Using the maximum frequency of 40MHz, valid values of M are 50 ≤ M ≤ 140. TABLE 7. CRYSTAL CHARACTERISTICS “3.3V Output Load Test Circuit”.

©2016 Integrated Device Technology, Inc Revision C January 8, 20167 TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units FMAX Output Frequency 350 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3 23 35 ps tjit(per) Period Jitter, RMS; NOTE 1 8 ps tsk(o) Output Skew; NOTE 2, 3 16 30 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps tS Setup Time M to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns tH Hold Time M to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle fOUT > 125MHz 48 50 52 % fOUT ≤ 125MHz 49 50 51 % tLOCK PLL Lock Time 1m s See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units FMAX Output Frequency 350 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3 23 35 ps tjit(per) Period Jitter, RMS; NOTE 1 7 ps tsk(o) Output Skew; NOTE 2, 3 16 35 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps tS Setup Time M to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns tH Hold Time M to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle fOUT > 125MHz 48 50 52 % fOUT ≤ 125MHz 49 50 51 % tLOCK PLL Lock Time 1m s See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision C January 8, 20168 PARAMETER MEASUREMENT INFORMATION PERIOD JITTER CYCLE-TO-CYCLE JITTEROUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

©2016 Integrated Device Technology, Inc Revision C January 8, 20169 The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR 3.3V LVPECL OUTPUTS

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 84314 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 Ω resistor along with a 10 µF and a .01 µF bypass capacitor should be connected to each VCCA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 2. POWER SUPPLY FILTERING

Figure 5. CRYSTAL INPUt INTERFACE values can be slightly adjusted for different board layouts.

©2016 Integrated Device Technology, Inc Revision C January 8, 201611 The schematic of the 84314 layout example used in this layout guideline is shown in Figure 6A. The 84314 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the LAYOUT GUIDELINE FIGURE 6A. SCHEMATIC OF 3.3V/3.3V RECOMMENDED LAYOUT actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. Logic Input Pin Examples Zo = 50 Ohm VCC ICS84314 VEE VCC VCCO nQ0 nQ1 nQ2 nQ3 VCCO MR S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK VCO_SEL nP_LOAD XTAL2 XTAL1 RD1 Not Install Zo = 50 Ohm C16 10u VCC C11 0.01u VCC 0.1u To Logic Input pins Zo = 50 Ohm C7 (Option) 0.1u C6 (Option) 0.1u VCC Set Logic Input to '0' To Logic Input pins 0.1u Set Logic Input to '1' VCCA VCC=3.3V VCC RU1 RU2 Not Install 0.1u RD2 VCC Zo = 50 Ohm

©2016 Integrated Device Technology, Inc Revision C January 8, 201612 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15 as close as pos- sible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with V CC, insert the RC fi lter R7, C11, and C16 in between. Place this RC fi lter as close to the VCCA as possible. CLOCK TRACES AND TERMINATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.  The traces with 50 Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.  Keep the clock trace on the same layer. Whenever pos- sible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality.  To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace.  Make sure no other signal trace is routed between th clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL1) and 26 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. FIGURE 6B. PCB BOARD LAYOUT FOR 84314

This section provides information on power dissipation and junction temperature for the 84314. Equations and example calculations are also provided. The total power dissipation for the 84314 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.7mW
• Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 519.7mW + 120mW = 639.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 9. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 10. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 11. PACKAGE DIMENSIONS

TABLE 12. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision C January 8, 201618 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T5C 6 13 - 14 LVPECL table - changed VOH max. from VCC - 1.0V to VCC - 0.9V. Changed equations in Power Considerations to correlate with Table 5C. 2/4/04 C T5B T12 LVCMOS/LVTTL TEST_CLK changed to LVCMOS TEST_CLK. Added Lead-Free bullet . Pin Descriptions Table - Pin 24, TEST_CLK, description changed from LVC- MOS/LVTTL interface levels to LVCMOS interface levels. LVCMOS DC Characteristics - TEST_CLK VIH (min.) changed from 2V to 2.35V; VIL (max.) changed from 1.3V to 0.95V. Added Lead-Free part number to Ordering Information Table. 11/5/04 C T5B 5 LVCMOS DC Characteristics Table - added V IH/VIL NOTE 1. 1/27/05 C T12 General Description - Removed ICS Chip and Hiperclocks. Ordering Information - Removed leaded parts, removed 1000 from tape and reel, and removed the LF note below the table. Added contacts page. Updated data sheet header and footer. 1/8/16

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