8430S10BYI-02LF | DigiCamel IC Datasheet

Online Datasheet

Read 8430S10BYI-02LF online.

8430S10I-02 IDT | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 31

Technical content

Features

One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels
Nine LVCMOS/ LVTTL outputs, 20 typical output impedance
Selectable external crystal or differential (single-ended) input source
Crystal oscillator interface designed for 25MHz, parallel resonant crystal
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
Power output supply modes LVDS and LVPECL – full 3.3V LVCMOS – full 3.3V or mi xed 3.3V core/2.5V output
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package Pin Assignment 13 14 15 16 17 18 19 20 21 22 23 24 QC 48 47 46 45 44 43 42 41 40 39 38 37 V QD0 QD1 GND GND VDDO _B QB0 VDD nOE_D GND nPLL_ SEL XTAL_IN XTAL_O U T nXTAL_S E L CLK nCLK nOE_C nOE_B GND VDD nOE_A nOE _REF CORE_SEL SPI_SEL1 SPI_SEL0 DDR_SEL1 DDR_SEL0 PCI_SEL1 PCI_SEL0 VDDA nLVDS_SEL 48 - Pin TQFP, E- Pad 7mm x 7mm x 1mm package body Y Package Top View nQA QA VDD VDDO _B QB1 DDO_CD36 VDDO_REF nOE_E GND GND VDDO_REF QE VDDO_E GND QREF2 QREF1 QREF0 ICS8430S10I-02 7mm x 7m x 1mm package body & Package Top View 8430S10I-02 Data Sheet Clock Generator for Cavium Processors

Table 1. Pin Descriptions 1, 13, 23 V DD Power Core supply pins. in high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. 39, 42, 46 GND Power Power supply ground. 4 nPLL_SEL Input Pulldown PLL bypass. When LOW, PLL is enable. When HIGH, PLL is bypassed. LVCMOS/LVTTL interface levels. XTAL_OUT Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. HIGH. LVCMOS/LVTTL interface levels. 8 CLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. 14 nOE_A Input Pulldown Active LOW output enable for B ank A outputs. LVCMOS/LVTTL interface levels. SPI_SEL0 Input Pulldown Selects the SPI PLL clock reference frequency. See Table 3D. PCI_SEL0 Input Pulldown Selects the PCI, PCI-X reference clock output frequency. See Table 3C. LVCMOS/LVTTL interface levels. DDR_SEL0 Input Pulldown Selects the DDR reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. 21, 22 nQA, QA Output Differential ou tput pair. Selectable between LVPECL and LVDS interface levels. 24 V DDA Power Analog supply pin. 25, 28 V DDO_B Power Bank B output supply pins. 3.3 V or 2.5V supply. 26, 27 QB1, QB0 Output Single-ended Bank B ou tputs. LVCMOS/LVTTL interface levels. impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled. LVCMOS/ LVTTL interface levels.

32 CORE_SEL Input Pulldown

33, 34 QD1, QD0 Output Single-end Bank D outputs. LVCMOS/LVTTL interface levels. 35 QC Output Single-end Bank C output. LVCMOS/LVTTL interface levels. 36 V DDO_CD Power Bank C and Bank D output supp ly pin. 3.3 V or 2.5V supply. Pin descriptions continue on the next page.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. 37 V DDO_E Power Bank E output supply pin. 3.3 V or 2.5V supply. 38 QE Output Single-end Bank E output. LVCMOS/LVTTL interface levels. 41, 48 V DDO_REF Power Bank QREF output supply pins. 3.3 V or 2.5V supply. Output Single-ended reference clock outputs. LVCMOS/LVTTL interface levels. high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels.

5©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Function Tables Table 3A. Control Input Function Table Table 3B. Control Input Function Table Table 3C. Control Input Function Table Table 3D. Control Input Function Table Table 3E. Control Input Function Table Input Output Frequency CORE_SEL QB[0:1] 0 50MHz (default) 1 33.333MHz Inputs Output Frequency DDR_SEL1 DDR_SEL0 QA, nQA 0 0 133.333MHz (default) 0 1 100.000MHz 1 0 83.333MHz 1 1 125.000MHz Inputs Output Frequency PCI_SEL1 PCI_SEL0 QC 0 0 133.333MHz (default) 0 1 100.000MHz 1 0 66.6667MHz 1 1 33.333MHz Inputs Output Frequency SPI_SEL1 SPI_SEL0 QD[0:1] 0 0 100.000MHz (default) 0 1 125.000MHz 1 0 80.000MHz Input Output Levels nLVDS_SEL QA, nQA

0 LVDS (default)

1 LVPECL

6©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVCMOS Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF. Table 4B. LVCMOS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 33.1°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.25 3.3 V DD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 180 mA IDDA Analog Supply Current 25 mA IDDO_X Output Supply Current No Load, CLK selected 60 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.25 3.3 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 102 mA IDDA Analog Supply Current 25 mA IDDO_X Output Supply Current No Load, CLK selected 42 mA

7©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Table 4C. LVPECL Power Supply DC Characteristics, VDD = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4D. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4E. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.25 3.3 V DD V IEE Power Supply Current nLVDS_SEL = 1 180 mA IDDA Analog Supply Current 25 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.25 3.3 V DD V IDD Power Supply Current nLVDS_SEL = 0 192 mA IDDA Analog Supply Current 25 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2.2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current DDR_SEL[0:1], nPLL_SEL, nLVDS_SEL, PCI_SEL[0:1], nOE_REF, SPI_SEL[0:1], nOE_[A:E], nXTAL_SEL, CORE_SEL VDD = VIN = 3.465V 150 µA IIL Input Low Current DDR_SEL[0:1], nPLL_SEL, nLVDS_SEL, PCI_SEL[0:1], nOE_REF, SPI_SEL[0:1], nOE_[A:E], nXTAL_SEL, CORE_SEL VDD = 3.465V, VIN = 0V -10 µA VOH Output High Voltage VDDO_X = 3.465V, IOH = -12mA 2.6 V VDDO_X = 2.625V, IOH = -12mA 1.8 V VOL Output Low Voltage VDDO_X = 3.465V, IOL = 12mA 0.65 V VDDO_X = 2.625V, IOL = 12mA 0.55 V

NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH. NOTE 1: Outputs terminated with 50 to VDD – 2V. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at maximum fOUT unless noted otherwise. NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_REF/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

10©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Typical Phase Noise at 125MHz (QE output) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.72ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

11©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Typical Phase Noise at 25MHz (QREF output) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 25MHz RMS Phase Jitter (Random) 10kHz to 5MHz = 0.58ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

12©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/3.3V LVPECL Output Load AC Test Circuit Differential Input Level 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 3.3V Core/3.3V LVDS Output Load AC Test Circuit LVCMOS Part-to-Part Skew SCOPE Qx GND -1.65V±5% VDDO_X 1.65V±5% VDD, VDDA 1.65V±5% -1.3V±0.165V VDDA VDD nCLK CLK VDD GND V CMR Cross Points VPP SCOPE Qx GND -1.25V±5% VDDO_X 2.05V±5% 1.25V±5% VDD VDDA 2.05V±5% 3.3V ±5% VDDA VDD tsk(pp) VDDOX VDDOX Part 1 Part 2 Qx Qy

13©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information, continued Differential Cycle-to-Cycle Jitter Period Jitter RMS Phase Jitter LVCMOS Cycle-to-Cycle Jitter Half Period Jitter LVCMOS Bank Skew (where X denotes QREF0 1, or 2) tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

(First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power ➤➤ ➤➤ VDDOX VDDOX VDDOX tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| QBx, QC, QDx, QE, QREFx ➤ ➤➤➤thalf period n thalf period n + 1 fo tjit(hper) = thalf period n — 1 2*fo QA nQA tsk(b) VDDOX VDDOX QREFx QREFx

14©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information, continued LVDS Output Rise/Fall Time LVCMOS Output Rise/Fall Time LVCMOS Output Duty Cycle/Pulse Width/Period LVPECL Output Rise/Fall Time Differential Output Duty Cycle/Pulse Width/Period Lock Time 20% 80% 80% 20% tR tF VOD QA nQA 20% 80% 80% 20% tR tF QBx, QC, QDx, QE, QREFx QBx, QC, QDx, QE, QREFx QA nQA QA nQA Output-to-Input Phase LockLock Time Not to Scale VDD GND Supply Voltage Output 60% of VDD

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) additional protection, a 1k  resistor can be tied from CLK to ground. should either be left floating or terminated.

22©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Power Considerations (LVCMOS/LVDS Outputs) This section provides information on power dissipation and junction temperature for the 8430S10I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8430S10I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation Power (core, LVDS) = V DD_MAX * (IDD + IDDA) = 3.465V * (192mA + 25mA) = 751.9mW LVCMOS Output Power Dissipation Output Impedance R OUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.80mA Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.80mA)2 = 12.3mW per output Total Power Dissipation on the R OUT Total Power (ROUT) = 12.3mW * 9 = 110.7mW Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output Total Power (133MHz) = 16mW * 6 = 96mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW Total Power Dissipation Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (133MHz) + Total Power (25MHz) = 751.9mW + 110.7mW + 96mW + 9mW = 967.6mW

23©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.968W * 33.1°C/W = 117°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7A. Thermal Resistance JA for 48 Lead TQFP, EPAD Forced Convection JA Vs. Air Flow Meters per Second 01 2 .5 Multi-Layer PCB, JEDEC Standard Test Boards 33.1°C/W 27.2°C/W 25.7°C/W

24©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Power Considerations (LVCMOS/LVPECL Outputs) This section provides information on power dissipation and junction temperature for the 8430S10I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8430S10I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation Power (core) _MAX = VDD_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW Power (output) _MAX = 30mW/Loaded Output Pair LVCMOS Output Power Dissipation Output Impedance R OUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.80mA Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.80mA)2 = 12.3mW per output Total Power Dissipation on the R OUT Total Power (ROUT) = 12.3mW * 9 = 110.7mW Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output Total Power (133MHz) = 16mW * 6 = 96mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW Total Power Dissipation Total Power = Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (133MHz) + Total Power (25MHz) = 623.7mW + 30mW + 110.7mW + 96mW + 9mW = 869.4mW

25©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7B. Thermal Resistance JA for 48 Lead TQFP, EPAD Forced Convection JA Vs. Air Flow Meters per Second 01 2 .5 Multi-Layer PCB, JEDEC Standard Test Boards 33.1°C/W 27.2°C/W 25.7°C/W

Table 8. JA vs. Air Flow Table for a 48 Lead TQFP, EPAD

Table 9. Package Dimensions 48L TQFP, EPAD

0.20 TAB

Ordering Information

Table 10. Ordering Information

30©2016 Integrated Device Technology, Inc. October 4, 2016 8430S10I-02 Data Sheet Revision History Sheet Rev Table Page Description of Change Date B T6 9 AC Characteristics Table - added Lock Time parameter. Added Lock Time measurement drawing. 11/2/09 C T4F Features section - corrected Differential Input bullet (deleted HCSL and LVHSTL levels). Block Diagram - corrected naming convention for SPI4_SEL1:0 to SPI_SEL1:0. Differential DC Characteristics Table - corrected VCMR levels from 0.5V min / VDD - 0.85V max to 1.2V min / VDD max. Deleted Power Supply Filtering Technique application note (see Schematic Example). Updated Wiring the Differential Input to Accept Single-ended Levels application note. Corrected Differential Clock Input Interface application note (deleted HCSL and LVHSTL levels). Deleted Crystal Input Interface application note (see Schematic Example). Updated Overdriving the XTAL Interface application note. Updated LVDS Driver Termination application note. Updated Schematic Example application note and diagram. Corrected D3/E3 dimensions. Updated Package Outline. 1/17/11 C Removed ICS from part number where needed. Updated header and footer. 10/4/16

31©2016 Integrated Device Technology, Inc. October 4, 2016 DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products an d/or specifications described h erein at any time, without notice, at ID T's sole discretion. Performance spec- ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without represent ation or warranty of any ki nd, whether express or imp lied, including, but not lim ited to, the suitability of IDT's product s for any particular purpose, an implied warranty of merchantability, or non-infringement of the inte llectual property rights of others. This docum ent is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other c ountries. Other trademarks used herein are the property of IDT or their respective third party owners. For datas heet type definitions and a glossary of common terms, visit Tech Support www.IDT.com/go/supp ort Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com

Product Information

8430S10BYI-02LF specifications and overview.

Summary

Clock Generator for Cavium Processors

Description

Clock Generator for Cavium Processors

Source title 8430S10BYI-02LF Datasheet(PDF) - Integrated Device Technology

Related Parts

More parts from the same family.

Browse manufacturer