8430S07AKILF | DigiCamel IC Datasheet

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ICS8430S07I IDT | Alldatasheet

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Features

One selectable differential LVPECL output pair for DDR 533/400/667
Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock references for GbE PHY
Selectable external crystal or differential (single-ended) input source
Crystal oscillator interface designed for 25MHz, parallel resonant crystal
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.78ps (typical), QD output
Output supply: LVPECL – 3.3V Core LVCMOS – Core/Output 3.3V/3.3V 3.3V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package HiPerClockS™ ICS Pin Assignment 91 0 1 1 12 13 14 15 16 32 31 30 29 28 27 26 25 VDD nPLL _SEL XTAL _IN XTAL _OUT nXTAL _SEL CLK nCLK GND QC GND GND QA nQA VDDO _B VDDO_C MR/ nOE_REF CORE _SEL DDR_SEL1 DDR_SEL0 VDDA PCI_SEL0 PCI_SEL1 VDDO_REF QREF0 QREF1 QREF2 GND QD VDDO_D ICS8430S07I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View VDD QB VDDO_REF

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 2 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Block Diagram 25MHz CLK nCLK PLL OSC nPLL_SEL 025MHz XTAL_IN XTAL_OUT 0 = 50.000MHz 1 = 33.333MHz 00 = 133.333MHz 01 = 100.000MHz 10 = 83.333MHz 11 = 125.000MHz Processor Core Clock (LVCMOS) DDR533, DDR400, or DDR667 Reference Clock (LVPECL) 125MHz GbE CLK 25MHz GbE CLK 00 = 133.333MHz 01 = 100.000MHz 10 = 66.667MHz 11 = 33.333MHz PCI or PCI-X Clock (LVCMOS) Gigabit Ethernet MAC Clock (LVCMOS) \\ Gigabit Ethernet / PHY Clocks / (LVCMOS) nXTAL_SEL QB QA nQA QC QD QREF0 QREF1 QREF2 CORE_SEL DDR_SEL1:0 PCI_SEL1:0 Clock Output Control Logic MR/nOE_REF PD PD PD PU/PD PD PD PD PD

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 3 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 15 V DD Power Core supply pins. the PLL. LVCMOS/LVTTL interface levels. when HIGH. LVCMOS/LVTTL interface levels. 6 CLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 8, 20, 21, 27 GND Power Power supply ground. PCI_SEL0 Input Pulldown Selects the PCI/PCI-X reference clock output frequency. See Table 3C. LVCMOS/LVTTL interface levels. DDR_SEL0 Input Pulldown Selects the DDR reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. 13, 14 nQA, QA Output Differential outp ut pair. LVPECL interface levels. 16 V DDA Power Analog supply pin. 17 V DDO_B Power Bank B output supply pin. 3.3 V or 2.5V supply. Output Single-ended outputs. LVCM OS/LVTTL interface levels.

19 MR/nOE_REF Input Pulldown

(HI-Z). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/ LVTTL interface levels.

22 CORE_SEL Input Pulldown

50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. DDO_C Power Bank C output supply pin. 3.3 V or 2.5V supply. 25 V DDO_D Power Bank D output supply pin. 3.3 V or 2.5V supply. 28, 32 V DDO_REF Power REF bank output supply pins. 3.3 V or 2.5V supply.

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 5 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF . NOTE: IDDO_X = IDDO_B, IDDO_C, IDDO_D and IDDO_REF . Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF . NOTE: IDDO_X = IDDO_B, IDDO_C, IDDO_D and IDDO_REF . Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to V DD + 0.5V Outputs, IO (LVPECL) Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 39.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 170 mA IDDA Analog Supply Current 20 mA IDDO_X Output Supply Current 25 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 160 mA IDDA Analog Supply Current 20 mA IDDO_X Output Supply Current 20 mA

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 6 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50Ω to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram. Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50Ω to VDD – 2V. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], DDR_SEL[0:1], MR/nOE_REF V DD = VIN = 3.465V 150 µA IIL Input Low Current nPLL_SEL, CORE_SEL, nXTAL_SEL, PCI_SEL[0:1], DDR_SEL[0:1], MR/nOE_REF V DD = 3.465V, VIN = 0V -10 µA VOH Output High Voltage; NOTE 1 VDDO_X = 3.465V 2.6 V VDDO_X = 2.625V 1.8 V VOL Output Low Voltage: NOTE 1 V DDO_X = 3.465V or 2.625V 0.6 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK/nCLK V DD = VIN = 3.465V 150 µA IIL Input Low Current CLK V DD = 3.465V, VIN = 0V -10 µA nCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 V DD – 0.85 V Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V DD – 1.4 V DD – 0.8 V VOL Output Low Voltage; NOTE 1 V DD – 2.0 V DD – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.55 1.0 V

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 8 ©2009 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: All outputs running at corresponding fMAX.

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 9 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Typical Phase Noise at 125MHz (QD output @ 3.3V) Typical Phase Noise at 25MHz (QREF output @ 3.3V) GbE Filter Phase Noise Result by adding a GbE filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.78ps (typical) Noise Power dBc Hz Offset Frequency (Hz) GbE Filter Phase Noise Result by adding a GbE filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.73ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 10 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information 3.3V Core/3.3V LVPECL Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Half Period Jitter 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Differential Input Level Period Jitter SCOPE Qx nQx LVPECL VEE -1.3V±0.165V VDDA VDD SCOPE Qx GND LVCMOS -1.25V±5% VDDO_X 2.05V±5% 1.25V±5% VDD VDDA 2.05V±5% ➤ ➤➤➤thalf period n thalf period n + 1 fo tjit(hper) = thalf period n — 1 2*fo QA nQA SCOPE QxLVCMOS GND -1.65V±5% VDDO_X 1.65V±5% VDD, VDDA 1.65V±5% nCLK CLK VDD GND V CMR Cross Points V PP VOH VREF VOL Mean Period (First edge after trigger) 10,000 cycles Reference Point (Trigger Edge) Histogram t jit (pk-pk)

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 11 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information, continued LVCMOS Bank Skew LVPECL Cycle-to-Cycle Jitter RMS Phase Jitter LVCMOS Part-to-Part Skew LVCMOS Cycle-to-Cycle Jitter Output Rise/Fall Time tsk(b) VDDO_REF VDDO_REF QREF[0:2] QREF[0:2] ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tsk(pp) VDDO_REF VDDO_REF Part 1 Part 2 Q_REFx Q_REFy ➤➤ ➤➤ VDDOX VDDOX VDDOX tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| QB:QD, QREF[0:2] 20% 80% 80% 20% tR tF VSWING QA:QD, QREF[0:2] nQA

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 13 ©2009 Integrated Device Technology, Inc. capacitor be connected to the VDDA pin. Figure 2. Power Supply Filtering additional protection, a 1kΩ resistor can be tied from CLK to ground. should either be left floating or terminated.

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 16 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output pair is low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 6A. 3.3V LVPECL Output Termination Figure 6B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 17 ©2009 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 19 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Power Considerations This section provides information on power dissipation and junction temperature for the ICS8430S07I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430S07I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation Power (core) _MAX = VDD_MAX * (IEE_MAX + IDDA + IDDO) = 3.465V * (170mA + 20mA + 25mA) = 744.98mW Power (output) _MAX = 30mW/Loaded Output Pair LVCMOS Output Power Dissipation Output Impedance R OUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.7mA Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15Ω * (26.7mA)2 = 10.7mW per output Total Power Dissipation on the R OUT Total Power (ROUT) = 10.7mW * 6 = 64.2mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.5mW per output Total Power (25MHz) = 1.5mW * 3 = 4.5mW Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 4pF * 133MHz * (3.465V)2 = 8mW per output Total Power (133MHz) = 8mW * 3 = 24mW Total Power Dissipation Total Power = Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (25MHz) + Total Power (125MHz) = 745mW + 30mW + 64.2mW + 4.5mW + 24mW = 867.7mW

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 20 ©2009 Integrated Device Technology, Inc. 125°C ensures that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 9. Figure 9. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Type A: Chamfer on the paddle (near pin 1)
Type B: Dummy pad between pin 1 and N.
Type C: Mouse bite on the paddle (near pin 1)

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009 25 ©2009 Integrated Device Technology, Inc. ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Revision History Sheet Rev Table Page Description of Change Date

ICS8430S07I Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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Product Information

8430S07AKILF specifications and overview.

Summary

Clock Generator for Cavium Processors

Description

Clock Generator for Cavium Processors

Source title 8430S07AKILF Datasheet(PDF) - Integrated Device Technology

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