8430B-71

8430B-71 RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
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700MHZ, Low Jitter, Crystal Interface LVCMOS-to-3.3V LVPECL Frequency Synthesizer 8430B-71 Data Sheet ©2015 Integrated Device Technology, Inc November 30, 20151 GENERAL DESCRIPTION The 8430B-71 is a general purpose, dual output Crystal/ LVCMOS-to-3.3V Differential LVPECL High Frequency Syn- thesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The 8430B-71 has a selectable crystal oscillator interface or LVCMOS TEST_CLK. The VCO operates at a frequency range of 250MHz to 700MHz. With the output configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved using a 16MHz crystal or test clock. Output frequencies up to 700MHz can be programmed using the serial or parallel inter- faces to the confi guration logic. The low jitter and frequency range of the 8430B-71 make it an ideal clock generator for most clock tree applications. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS TEST_CLK
• Output frequency up to 700MHz
• Crystal input frequency range: 12MHz to 27MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter: 9ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Replaces 8430-71
• Available in lead-free (RoHS 6) package 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_OUT TEST_CLK XTAL_SEL V CCA S_LOAD S_DATA S_CLOCK MR V EE VEE nFOUT0 FOUT0 V CCO nFOUT1 FOUT1 V CC TEST XTAL_IN nP_LOAD VCO_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS8430B-71 OSC Phase Detector VCO Configuration Interface Logic ÷16 PLL FOUT0 nFOUT0 FOUT0 nFOUT0 TEST S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 MR XTAL_OUT XTAL_IN XTAL_SEL VCO_SEL TEST_CLK N0:N2 PD PD PU PU PD PD PD PD

Characteristics, Table 5, NOTE 1. LVPECL output buffers. The divider provides a 50% output duty cycle. put modes to program the M divider and N output divider. FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

TABLE 1. PIN DESCRIPTIONS LOAD input. LVCMOS / LVTTL interface levels.

4 M8 Input Pullup

9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Power Core power supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interface levels.

17 MR Input Pulldown

M, N, and T values. LVCMOS / LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register

on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. CLOCK. LVCMOS / LVTTL interface levels.

22 XTAL_SEL Input Pullup

PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. N output divider value. LVCMOS / LVTTL interface levels. 27 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

©2015 Integrated Device Technology, Inc November 30, 20154 TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 2 5 001111101 2 5 2 1 2 6 001111110 2 5 4 1 2 7 001111111 2 5 6 1 2 8 010000000 6 9 6 3 4 8 101011100 6 9 8 3 4 9 101011101 7 0 0 3 5 0 101011110 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 16MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value FOUT0, nFOUT0 Output Frequency (MHz) N2 N1 N0 Minimum Maximum 0 0 0 2 125 350 0 0 1 4 62.5 175 0 1 0 8 31.25 87.5 0 1 1 16 15.625 43.75 1 0 0 1 250 700 1 0 1 2 125 350 1 1 0 4 62.5 175 1 1 1 8 31.25 87.5 Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LH X XH ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition

©2015 Integrated Device Technology, Inc November 30, 20155 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage 3.135 3.3 3.465 V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 140 mA I CCA Analog Supply Current 15 mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C TABLE 4C. LVPECL DC CHARACTERISTICS, V CC = V CCA = V CCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V OH Output High Voltage; NOTE 1 V CC - 1.4 V CC - 0.9 V V OL Output Low Voltage; NOTE 1 V CC - 2.0 V CC - 1.7 V V SWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50W to V CCO - 2V. See “Parameter Measurement Information” section, “3.3V Output Load Test Circuit” fi gure. Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage TEST_CLK; NOTE 1 2.35 V CC + 0.3 V VCO_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, MR, M0:M8, N0:N2, XTAL_SEL CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current M0-M7, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD V CC = V IN = 3.465V 150 µA M8, N2, XTAL_SEL, VCO_SEL V CC = V IN = 3.465V 5 µA TEST_CLK V CC = V IN = 3.465V 200 µA I IL Input Low Current M0-M7, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD V CC = 3.465V, V IN = 0V -5 µA TEST_CLK, M8, N2, XTAL_SEL, VCO_SEL V CC = 3.465V, V IN = 0V -150 µA V OH Output High Voltage TEST; NOTE 2 2.6 V V OL Output Low Voltage TEST; NOTE 2 0.5 V NOTE 1: Characterized with 1ns input edge rate. NOTE 2: Outputs terminated with 50Ω to V CCO /2.

TABLE 7. AC CHARACTERISTICS, V See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 5. INPUT CHARACTERISTICS, V 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466. Using the maximum frequency of 27MHz, valid values of M are 75 ≤ M ≤ 207. TABLE 6. CRYSTAL CHARACTERISTICS

©2015 Integrated Device Technology, Inc November 30, 20157 PARAMETER MEASUREMENT INFORMATION PERIOD JITTER OUTPUT SKEW3.3V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

©2015 Integrated Device Technology, Inc November 30, 20158 As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 8430B-71 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA , and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be connected to each V CCA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING

APPLICATION INFORMATION

INPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left fl oating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. TEST_CLK I NPUT: For applications not requiring the use of the test clock, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS C ONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

©2015 Integrated Device Technology, Inc November 30, 201510 The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS

©2015 Integrated Device Technology, Inc November 30, 201511 FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT S_LOAD TL1 Zo = 50 Ohm C14 0.1u S_CLOCK VCC VCC C16 10u 125 FOUT REF_IN TL2 Zo = 50 Ohm ICS8430B-71 VEE TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE MR S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK X_OU T VCO_SEL nP_LOAD X_IN 125 C11 0.01u IN+ XTAL_SEL C15 0.1u IN- FOUTN VCC VCCA VCC S_DATA LAYOUT GUIDELINE The schematic of the 8430B-71 layout example used in this layout guideline is shown in Figure 5A. The 8430B-71 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board.

©2015 Integrated Device Technology, Inc November 30, 201512 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If V CCA shares the same power supply with V CC , insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the V CCA as possible. CLOCK TRACES AND TERMINATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.  The traces with 50 Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.  Keep the clock trace on the same layer. Whenever pos- sible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality.  To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace.  Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. FIGURE 5B. PCB BOARD LAYOUT FOR 8430B-71

This section provides information on power dissipation and junction temperature for the 8430B-71. Equations and example calculations are also provided. The total power dissipation for the 8430B-71 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. and the type of board (single layer or multi-layer). NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 9. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 10. PACKAGE DIMENSIONS

TABLE 11. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc November 30, 201518 REVISION HISTORY SHEET Rev Table Page Description of Change Date A Updated data sheet format. 11/30/15

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