8430AYI-61LFT

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500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequeny Synthesizer 8430I-61 DATA SHEET 8430I-61 REVISION D 10/15/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 8430I-61 is a general purpose, dual output Crystal-to-3.3V, 2.5V Differential LVPECL High Frequency Synthesizer . The 8430I-61 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 500MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the confi guration logic. Frequency steps as small as 1MHz can be achieved using a 16MHz crystal or TEST_CLK. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• Dual differential 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 20.83MHz to 500MHz
• Crystal input frequency range: 14MHz to 27MHz
• VCO range: 250MHz to 500MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter: 6ps (maximum)
• Cycle-to-cycle jitter: 30ps (maximum)
• Supply voltage modes: VCC/VCCA/VCCO 3.3/3.3/3.3 3.3/3.3/2.5
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_OUT TEST_CLK XTAL_SEL V CCA S_LOAD S_DATA S_CLOCK MR V EE VEE nFOUT0 FOUT0 V CCO nFOUT1 FOUT1 V CC TEST XTAL_IN nP_LOAD VCO_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS8430I-61

2 REVISION D 10/15/15

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS Frequency Characteristics, Table 5, NOTE 1. quires no external components for setting the loop bandwidth. also applied to the phase detector.

16 MfVCO =

TABLE 1. PIN DESCRIPTIONS 8, 16 V EE Power Negative supply pins. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS interface levels. 10 V CC Power Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. LVPECL interface levels. 13 V CCO Power Output supply pin for LVPECL outputs. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. LVPECL interface levels.

17 MR Input Pulldown

and T values. LVCMOS / LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on

the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. of S_CLOCK. LVCMOS / LVTTL interface levels. MOS / LVTTL interface levels. CCA Power Analog supply pin.

22 XTAL_SEL Input Pullup

LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. IN Input Crystal oscillator interface. XTAL_IN is the input. N output divider value. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8430I-61 DATA SHEET

4 REVISION D 10/15/15

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LH X XH ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 2 5 0 011111010 2 5 1 2 5 1 011111011 2 5 2 2 5 2 011111100 2 5 3 2 5 3 011111101 4 9 8 4 9 8 111110010 4 9 9 4 9 9 111110011 5 0 0 5 0 0 111110100 NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz. Inputs N Divider Value Output Frequency (MHz) N2 N1 N0 Minimum Maximum 0 0 0 1 250 500 0 0 1 1.5 166.66 333.33 0 1 0 2 125 250 0 1 1 3 83.33 166.66 1 0 0 4 62.5 125 1 0 1 6 41.66 83.33 1 1 0 8 31.25 62.5 1 1 1 12 20.83 41.66

5 500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IEE Power Supply Current 155 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage M0:M8, N0:N2, MR, S_LOAD, S_DATA, S_CLOCK, nP_ LOAD, VCO_SEL, XTAL_SEL CC + 0.3 V TEST_CLK 2 V CC + 0.3 V VIL Input Low Voltage M0:M8, N0:N2, MR, S_LOAD, S_DATA, S_CLOCK, nP_ LOAD, VCO_SEL, XTAL_SEL -0.3 0.8 V TEST_CLK -0.3 1.3 V I IH Input High Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = VIN = 3.465V 150 µA M5, XTAL_SEL, VCO_SEL V CC = VIN = 3.465V 5 µA IIL Input Low Current M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, nP_LOAD V CC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 V CC = 3.465V 2.6 V VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCC/2.

6 REVISION D 10/15/15

the 250MHz to 500MHz range. Using the minimum input frequency of 14MHz, valid values of M are 286 ≤ M ≤ 511. Using the maximum input frequency of 27MHz, valid values of M are 149 ≤ M ≤ 296. TABLE 6. CRYSTAL CHARACTERISTICS All AC parameters guaranteed for VCC=VCCA=VCCO=3.3V ±5%. “3.3V Output Load Test Circuit” fi gure. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C

7 500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units FOUT Output Frequency 20.83 500 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 N ≠ 1.5 30 ps N = 1.5 100 ps tjit(per) Period Jitter, RMS; NOTE 1 N ≠ 1.5 6p s tsk(o) Output Skew; NOTE 2, 3 15 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns tH Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle Even N divides 48 52 % Odd N divides 45 55 % tLOCK PLL Lock Time 1m s See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units FOUT Output Frequency 20.83 500 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 N ≠ 1.5 35 ps N = 1.5 140 ps tjit(per) Period Jitter, RMS; NOTE 1 N ≠ 1.5 6p s tsk(o) Output Skew; NOTE 2, 3 30 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns tH Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle Even N divides 47 53 % Odd N divides 45 55 % tLOCK PLL Lock Time 1m s See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points.

500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8430I-61 DATA SHEET

8 REVISION D 10/15/15

PARAMETER MEASUREMENT INFORMATION PERIOD JITTER 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME OUTPUT SKEW CYCLE-TO-CYCLE JITTER

10 REVISION D 10/15/15

tied from XTAL_IN to ground. 1kΩ resistor can be tied from the TEST_CLK to ground. protection. A 1kΩ resistor can be used. output pair should either be left fl oating or terminated. FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE and R2 in parallel should equal the transmission line impedance. also be accomplished by removing R1 and making R2 50Ω.

11 500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR 3.3V LVPECL OUTPUTS

500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8430I-61 DATA SHEET

12 REVISION D 10/15/15

TERMINATION FOR 2.5V LVPECL OUTPUT Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to V CC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE Zo = 50 Ohm VCCO=2.5V Zo = 50 Ohm 2.5V 2,5V LVPECL Driver FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE VCCO=2.5V Zo = 50 Ohm 2,5V LVPECL Driver Zo = 50 Ohm 2.5V FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 2.5V 2,5V LVPECL Driver 250 Zo = 50 Ohm Zo = 50 Ohm 62.5 2.5V 250 VCCO=2.5V

13 500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The schematic of the 8430I-61 layout example used in this layout guideline is shown in Figure 7A. The 8430I-61 recommended PCB board layout for this example is shown in Figure 7B. This layout example is used as a general guideline. The layout in the LAYOUT GUIDELINE FIGURE 7A. SCHEMATIC OF RECOMMENDED LAYOUT actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. VCC To Logic Input pins 125 Logic Input Pin Examples VCC=3.3V Zo = 50 Ohm RU2 SP VCC Zo = 50 Ohm C15 0.1u Set Logic Input to '0' VCC C14 0.1u RU1 ICS8430-61 VEE TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE MR S_CLOCK S_DATA S_LOAD VCCA nXTAL_SEL REF_IN XTAL_OUT VCO_SEL nP_LOAD XTAL_IN SP = Spare Pads RD1 SP To Logic Input pins RD2 VCC C11 0.01u C16 10u 125 VCC VCCA Set Logic Input to '1'

500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8430I-61 DATA SHEET

14 REVISION D 10/15/15

The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15 as close as pos- sible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If V CCA shares the same power supply with V CC, insert the RC fi lter R7, C11, and C16 in between. Place this RC fi lter as close to the V CCA pin as possible. CLOCK TRACES AND TERMINATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The traces with 50 Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock trace on the same layer. Whenever pos- sible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace.
• Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.FIGURE 7B. PCB BOARD LAYOUT FOR 8430I-61

This section provides information on power dissipation and junction temperature for the 8430I-61. Equations and example calculations are also provided. The total power dissipation for the 8430I-61 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW
• Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION

16 REVISION D 10/15/15

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

18 REVISION D 10/15/15

TABLE 10. PACKAGE DIMENSIONS

TABLE 11. ORDERING INFORMATION trial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifi cations without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 8430I-61 DATA SHEET

20 REVISION D 10/15/15

Rev Table Page Description of Change Date A T7 Features Section - changed Supply Voltage bullet. AC Table - Added 3V Note. 10/21/04 B T4C T11 Features Section - added Lead-Free bullet. Supply voltage bullet added supply modes. Updated Parallel & Serial Load Operations Diagram. LVPECL DC Characteristics Table added “NOTE: All DC parameters...”. Crystal Characteristics Table - added Drive Level. Recommendations for Unused Input and Output Pins. Ordering Information Table - added Lead-Free part number and note. 7/12/05 B T11 Updated Output Load AC Test Circuit diagram. Updated Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free marking. 2/17/06 C T4A T7A T7B Pin Assignment - swapped pins 24 & 25. Pin Description table - pin 24 now XTAL_OUT and pin 25 now XTAL_IN. Power Supply table - changed V CCA from 3.465V max. to VCC max., and changed ICCA from 55mA max. to 15mA max. Added 2.5V output. 3.3V AC Characteristics table - added test condition to Period Jitter. Added 3.3V/2.5V AC Characteristics table. Corrected 3.3V Output Load AC Test Circuit Diagram. Added 3.3V/2.5V Output Load AC Test Circuit Diagram. Added LVCMOS to XTAL Interface section. Updated Schematic Layout. 6/2/06 D T11 19 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/27/10 Updated data sheet format. 10/15/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.