8430AY-62 | DigiCamel IC Datasheet

Online Datasheet

Read 8430AY-62 online.

ICS8430-62 IDT | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 23

Technical content

Features

Dual differential 3.3V or 2.5V LVPECL outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK
Output frequency range: 20.83MHz to 500MHz
Crystal input frequency range: 14MHz to 27MHz
VCO range: 250MHz to 500MHz
Parallel or serial interface for programming counter and output dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V or 3.3V core/2.5V output supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram HiPerClockS™ ICS OSC Phase Detector VCO Configuration Interface Logic ÷16 ÷1.5 ÷12 PLL FOUT0 nFOUT0 FOUT1 nFOUT1 TEST S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 MR XTAL_OUT XTAL_IN XTAL_SEL VCO_SEL REF_CLK N0:N2 Pulldown Pulldown Pullup Pullup Pulldown Pulldown Pulldown Pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VEE XTAL_OUT REF_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE VCO_SEL nP_LOAD XTAL_IN Pin Assignment ICS8430-62

32 Lead LQFP

7mm x 7mm x 1.4mm package body Y Package Top View

ICS8430AY-62 REVISION A JULY 2, 2009 2 ©2009 Integrated Device Technology, Inc. Characteristics, Table 5, NOTE 1. buffers. The divider provides a 50% output duty cycle. specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. the M divider and N output divider on each rising edge of S_CLOCK.

00 L O W

Figure 1. Parallel & Serial Load Operations

ICS8430AY-62 REVISION A JULY 2, 2009 3 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics M2, M3, M4 Input Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. 5, 7 N0, N2 Input Pulldown Determines output divider value as defined in Table 3C, Function Table. 8, 16 V EE Power Negative supply pins. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. 10 V CC Power Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output pair for t he synthesizer. LVPECL interface levels. 13 V CCO Power Output supply pin for LVPECL outputs. 14, 15 FOUT0, nFOUT0 Output Differential output pair for t he synthesizer. LVPECL interface levels.

17 MR Input Pulldown

go high. When Logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on the

rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 19 S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 20 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. CCA Power Analog supply pin.

22 XTAL_SEL Input Pullup

source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW. LVCMOS/LVTTL interface levels. 23 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. XTAL_IN Input Crystal oscillator interf ace. XTAL_IN is the input, XTAL_OUT is the output. divider, and when data present at N2:N0 sets the N output divider value. LVCMOS/LVTTL interface levels.

27 VCO_SEL Input Pullup

synthesizer is in bypass mode, when HIGH,synthesizer is in PLL mode. LVCMOS/LVTTL interface levels.

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 4 ©2009 Integrated Device Technology, Inc. Function Tables Table 3A. Parallel and Serial Mode Function Table NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition Table 3B. Programmable VCO Frequency Function Table NOTE 1: These M divide values and the resulting frequencies correspond to a REF_CLK or crystal frequency of 16MHz. Inputs ConditionsMR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces true outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LHX XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LHX X ↑ LD a t a Contents of the shift register are passed to the M divider and N output divider. LHX X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LHX XH ↑ Data S_DATA passed directly to M divider as it is clocked. VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 2 5 0 011111010 2 5 1 2 5 1 011111011 2 5 2 2 5 2 011111100 2 5 3 2 5 3 011111101 4 9 8 4 9 8 111110010 4 9 9 4 9 9 111110011 5 0 0 5 0 0 111110100

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 5 ©2009 Integrated Device Technology, Inc. Table 3C. Programmable Output Divider Function Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C Inputs N Divider Value Output Frequency (MHz) N2 N1 N0 Minimum Maximum 0001 2 5 0 5 0 0 0 0 1 1.5 166.66 333.33 0102 1 2 5 2 5 0 0113 8 3 . 3 3 1 6 6 . 6 6 1004 6 2 . 5 1 2 5 1016 4 1 . 6 6 8 3 . 3 3 1108 3 1 . 2 5 6 2 . 5 1 1 1 12 20.83 41.66 Item Rating Supply Voltage, V CC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 65.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.14 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IEE Power Supply Current 130 mA ICCA Analog Supply Current 14 mA

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 6 ©2009 Integrated Device Technology, Inc. Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VCCO = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. Table 4D. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current M[0:6], N0, N2, MR, S_CLOCK, REF_CLK, S_DATA, S_LOAD, nP_LOAD V CC = VIN = 3.465V 150 µA M7, M8, N1, XTAL_SEL, VCO_SEL VCC = VIN = 3.465V 5 µA IIL Input Low Current M[0:6], N0, N2, MR, S_CLOCK, REF_CLK, S_DATA, S_LOAD, nP_LOAD V CC = 3.465V, VIN = 0V -5 µA M7, M8, N1, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA VOH Output High Voltage TEST; NOTE 1 VCCO = 3.3V±% 2.6 V VCCO = 2.5V±5% 1.8 V VOL Output Low Voltage TEST; NOTE 1 V CCO = 3.3V±5% or 2.5V±5% 0.5 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Current; NOTE 1 V CCO – 1.4 V CCO – 0.9 µA VOL Output Low Current; NOTE 1 V CCO– 2.0 V CCO – 1.7 µA VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Current; NOTE 1 V CCO – 1.4 V CCO – 0.9 µA VOL Output Low Current; NOTE 1 V CCO– 2.0 V CCO – 1.5 µA VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V

ICS8430AY-62 REVISION A JULY 2, 2009 7 ©2009 Integrated Device Technology, Inc. Table 5. Input Characteristics, VCC = 3.3V±5%, VCCO = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C valid values of M are 149 ≤ M ≤ 296. Table 6. Crystal Characteristics

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 8 ©2009 Integrated Device Technology, Inc. Table 7A. AC Characteristics, VCC = VCCO = 3.3V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 20.83 500 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 N ≠ 1.5 35 ps N = 1.5 200 ps tjit(per) Period Jitter, RMS; NOTE 1 N ≠ 1.5 5 ps tsk(o) Output Skew; NOTE 2, 3 20 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns t H Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle Even N Dividers 48 52 % Odd N Dividers 43 57 % t LOCK PLL Lock time 10 ms

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 9 ©2009 Integrated Device Technology, Inc. Table 7B. AC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency 20.83 500 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 N ≠ 1.5 35 ps N = 1.5 200 ps tjit(per) Period Jitter, RMS; NOTE 1 N ≠ 1.5 6 ps tsk(o) Output Skew; NOTE 2, 3 20 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns t H Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle Even N Dividers 48 52 % Odd N Dividers 43 57 % t LOCK PLL Lock time 10 ms

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 10 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information 3.3/3.3V LVPECL Output Load AC Test Circuit Output Skew Cycle-to-Cycle Jitter 3.3V/2.5V LVPECL Output Load AC Test Circuit Period Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx LVPECL VEE VCC, -1.3V±0.165V VCCA VCCO tsk(o) nFOUTx FOUTx nFOUTy FOUTy ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

2.8V±0.04V -0.5V±0.125V VCC VCCA VCCO 2.8V±0.04V VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nFOUTx FOUTx tPW tPERIOD tPW tPERIOD odc = x 100%

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 11 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Rise/Fall Time

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8430-62 provides separate power supplies to isolate any high frequency switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. The 10Ω resistor can also be replaced by a ferrite bead. Figure 2. Power Supply Filtering 20% 80% 80% 20% tR tF VSWING nFOUTx FOUTx VCC VCCA 3.3V 10Ω 10µF.01µF .01µF

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 13 ©2009 Integrated Device Technology, Inc. Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: TEST Output The unused TEST output can be left floating. There should be no trace attached. LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 15 ©2009 Integrated Device Technology, Inc. Schematic Example The schematic of the ICS8430-62 layout example used in this layout guideline is shown in Figure 7A. The ICS8430-62 recommended PCB board layout for this example is shown in Figure 7B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. Figure 7A. ICS8430-62 Schematic of Recommended Layout C11 0.01u 125 Zo = 50 Ohm Zo = 50 Ohm C15 0.1u 125 C16 10u C14 0.1u VCC M51 M62 M73 M84 N05 N16 N27 VEE8 TEST9 VCC10 FOUT111 nFOUT112 VCCO13 FOUT014 nFOUT015 VEE16 MR 17S_CLOCK 18S_DATA 19S_LOAD 20VCCA 21XTAL_SEL 22REF_CLK 23XTAL_OU T 24 M4 32 M3 31 M2 30 M1 29 M0 28 VCO_SEL 27 nP_LOAD 26 XTAL_IN 25 VCC VCC VCCA RU1 1KRD1 SP VCC RU2 SPRD2 VCC To Logic Input pins Set Logic Input to '0' Set Logic Input to '1' Logic Input Pin Examples To Logic Input pins SP = Spare Pads VCC=3.3V

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 16 ©2009 Integrated Device Technology, Inc. The following component footprints are used in this layout example. All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If V CCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA pin as possible. Clock Traces and Termination The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. The traces with 50 Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace.Sharp angle turns cause the characteristic impedance to change on the transmission lines. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. Make sure no other signal traces are routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. Crystal The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. Figure 7B. PCB Board Layout for ICS8430-62 TL1, TL21N are 50 Ohm traces and equal length C16 PIN 1 C11 TL1 C14 TL1C15 R2 VIA Close to the input pins of the receiver TL1N GND TL1N VCCA VCC

ICS8430AY-62 REVISION A JULY 2, 2009 17 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8430-62. Equations and example calculations are also provided. The total power dissipation for the ICS8430-62 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for HiPerClockS devices is 125°C. a multi-layer board, the appropriate value is 65.7°C/W per Table 8 below. Table 8. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection

Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. Figure 8. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Ordering Information

Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8430AY-62 REVISION A JULY 2, 2009 22 ©2009 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A 1 Block Diagram - output labels were cut-off. 7/2/09

ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056

Product Information

8430AY-62 specifications and overview.

Summary

500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequency Synthesizer

Description

500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequency Synthesizer

Source title 8430AY-62 Datasheet(PDF) - Integrated Device Technology

Related Parts

More parts from the same family.

Browse manufacturer