DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
FemtoClock® Crystal-to-2.5V, 3.3V LVPECL Clock Multiplier 843081I-01 DATA SHEET 843081I-01 REVISION C 11/5/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843081I-01 is an Ethernet Clock Multiplier. The 843081I-01 accepts a crystal reference of 19.6MHz - 28MHz. The 843081I- 01 has excellent 1ps or lower phase jitter performance, over the 1.875MHz - 20MHz integration range. The 843081I-01 is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.
FEATURES
- One differential LVPECL output
- One crystal oscillator interface: 19.6MHz - 28MHz
- Output frequency range: 490MHz - 700MHz
- VCO range: 490MHz - 700MHz
- RMS phase jitter @ 625MHz using a 25MHz reference (1.875MHz - 20MHz): 0.32ps (typical)
- 3.3V or 2.5V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free RoHS compliant package For functional replacement part use 843071 843081I-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VCCA XTAL_OUT XTAL_IN VEE VCC Q nQ OE VCO 490 - 700 MHz Phase Detector M = ÷25 (fixed) OE XTAL_IN XTAL_OUT Q nQ BLOCK DIAGRAM PIN ASSIGNMENT FREQUENCY EXAMPLE FUNCTION TABLE Input M/N (Multiplier) Output Frequencies (MHz)XTAL (MHz) 20 25 500 25 25 625 28 25 700
2 REVISION C 11/5/15
TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 1V CCA Power Analog supply pin. 4V EE Power Negative supply pin. 5 OE Input Pullup Output enable pin. When HIGH, Q output is enabled. When LOW, forces Q to HiZ state. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. 8V CC Power Core supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
3 FEMTOCLOCKS ® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V ± 5%, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V ± 5% OR 2.5V ± 5%, TA = -40°C TO 85°C TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 72 mA ICCA Analog Supply Current 12 mA IEE Power Supply Current 78 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V ICC Power Supply Current 60 mA ICCA Analog Supply Current 12 mA IEE Power Supply Current 73 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.3V 2 V CC + 0.3 V VCC = 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V IIH Input High Current V CC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current V CC = 3.465V or 2.625V, VIN = 0V -150 µA
4 REVISION C 11/5/15
NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS NOTE 1: Please refer to the Phase Noise Plot following this section. NOTE 1: Please refer to the Phase Noise Plot following this section.
5 FEMTOCLOCKS ® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER TYPICAL PHASE NOISE AT 625MHZ @ 3.3V -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 200 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 200 TYPICAL PHASE NOISE AT 625MHZ @ 2.5V 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M Phase Noise Result by adding a Gb Ethernet Filter to raw data Raw Phase Noise Data Gb Ethernet Filter Phase Noise Result by adding a Gb Ethernet Filter to raw data Raw Phase Noise Data Gb Ethernet Filter
FEMTOCLOCKS® CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK MULTIPLIER 843081I-01 DATA SHEET
6 REVISION C 11/5/15
PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER
7 FEMTOCLOCKS ® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843081I-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be connected to each V CCA pin. The 10Ω resistor can also be replaced by a ferrite bead. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING Figure 2. CRYSTAL INPUt INTERFACE
FEMTOCLOCKS® CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK MULTIPLIER 843081I-01 DATA SHEET
8 REVISION C 11/5/15
TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
9 FEMTOCLOCKS® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat- ing 50Ω to V CC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLEFIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 Zo = 50 Ohm 250 2.5V 2,5V LVPECL Driver 62.5 250 Zo = 50 Ohm 2.5V VCC=2.5V Zo = 50 Ohm Zo = 50 Ohm 2,5V LVPECL Driver VCC=2.5V 2.5V 2,5V LVPECL Driver VCC=2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm
10 REVISION C 11/5/15
This section provides information on power dissipation and junction temperature for the 843081I-01. Equations and example calculations are also provided. The total power dissipation for the 843081I-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 78mA = 270.27mW
- Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 270.27mW + 30mW = 300.27mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = J unction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.300W * 90.5°C/W = 112°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
11 FEMTOCLOCKS ® CRYSTAL-TO-
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
12 REVISION C 11/5/15
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
13 FEMTOCLOCKS ® CRYSTAL-TO-
TABLE 8. PACKAGE DIMENSIONS
14 REVISION C 11/5/15
TABLE 9. ORDERING INFORMATION trial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifi cations without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
15 FEMTOCLOCKS ® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER REVISION HISTORY SHEET Rev Table Page Description of Change Date B T5A T5B Features Section - corrected RMS Phase Jitter value. 3.3V AC Characteristics Table - changed RMS Phase Jitter from 0.26ps typical to 0.32ps typical. 2.5V AC Characteristics Table - changed RMS Phase Jitter from 0.27ps typical to 0.39ps typical. Updated Typical Phase Noise Plots. Ordering Information Table - added lead-free marking. 1/23/06 CT 9 1 4 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/25/10 Updated data sheet format. 10/15/15 C 1 Product Discontinuation Notice - Last time buy expires November 2, 2016.
6024 Silver Creek Valley Road
San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.