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Technical content
Features
- One differential 3.3V or 2.5V LVPECL output
- Crystal oscillator interface,18pF parallel resonant crystal (20.833MHz – 28.3MHz)
- Output frequency range: 62.5MHz – 170MHz
- VCO range: 500MHz – 680MHz
- RMS phase jitter at 150MHz, using a 25MHz crystal (12kHz – 20MHz): 0.64ps (typical) @ 3.3V output
- RMS phase jitter at 159.375MHz, using a 26.5625MHz crystal (1.875MHz – 20MHz): 0.40ps (typical) @ 3.3V output
- Full 3.3V or 2.5V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Common Configuration Table - Serial ATA/Serial Attached SCSI Block Diagram Inputs Output Frequency (MHz)Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N 25 0 24 4 6 150 25 1 24 8 3 75 26.5625 0 24 4 6 159.375 OSC Phase Detector VCO 500MHz - 680MHz M = ÷24 (fixed) FREQ_SEL N 0 ÷4 1 ÷8 nQ0 PullupFREQ_SEL XTAL_IN XTAL_OUT VCCA XTAL_OUT XTAL_IN VEE VCC Q nQ FREQ_SEL Pin Assignment 843071
8 Lead TSSOP
4.40mm x 3.0mm package body
843071 DATA SHEET
Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2,Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V CCA Power Analog supply pin. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4V EE Power Negative supply pin. 5 FREQ_SEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential output pair. LVPECL interface levels. 8V CC Power Core supply pin.
REVISION C 10/19/15 3 FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC =V CCA = 3.3V ± 10%, VEE = 0V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VCC =V CCA =2 . 5 V±5 % ,VEE = 0V, TA = -40°C to 85°C Table 3C. LVCMOS/LVTTL DC Characteristics, VCC =V CCA = 3.3V ± 10%, 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65Ct o1 5 0C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.0 3.3 3.63 V VCCA Analog Supply Voltage 3.0 3.3 3.63 V ICC Power Supply Current 96 mA ICCA Analog Supply Current 12 mA IEE Power Supply Current 72 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V ICC Power Supply Current 72 mA ICCA Analog Supply Current 12 mA IEE Power Supply Current 72 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 3.3V 2 V CC + 0.3 V 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage 3.3V -0.3 0.8 V 2.5V -0.3 0.7 V IIH Input High Current V CC =V IN = 3.63V or 2.625V 5 µA IIL Input Low Current V CC = 3.63V or 2.625V, VIN = 0V -150 µA
NOTE 1: Outputs termination with 50 to VCC –2 V . Table 4. Crystal Characteristics has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots.
REVISION C 10/19/15 5 FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Typical Phase Noise at 75MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 75MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.64ps (typical) Noise Power dBc Hz Offset Frequency (Hz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -150 -110 -120 -130 -140 -160 -170 -180 -190 -200
FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 6 REVISION C 10/19/15 Typical Phase Noise at 150MHz (3.3V) Typical Phase Noise at 159.375MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 150MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.64ps (typical) Noise Power dBc Hz Offset Frequency (Hz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -150 -110 -120 -130 -140 -160 -170 -180 -190 -200 10Gb Fibre Channel Phase Noise Result by adding a 10Gb Fibre Channel to raw data Raw Phase Noise Data 159.375MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.404ps (typical) Noise Power dBc Hz Offset Frequency (Hz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -150 -110 -120 -130 -140 -160 -170 -180 -190
REVISION C 10/19/15 7 FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx VEE VCC, -1.3V ± 0.33V VCCA Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ Q SCOPE Qx nQx VEE VCC, -0.5V ± 0.125V VCCA nQ Q
Figure 1. Power Supply Filtering can be slightly adjusted for different board layouts. Figure 2. Crystal Input Interface
REVISION C 10/19/15 9 FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 10 REVISION C 10/19/15 Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 o =5 0 o =5 0 Input 3.3V 3.3V
REVISION C 10/19/15 11 FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC –2 V .F o rVCC = 2.5V, the VCC – 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5C. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V LVPECL Driver VCCO = 2.5V 2.5V 2.5V 50 50 250 250 62.5 62.5 2.5V LVPECL Driver VCCO = 2.5V 2.5V 50 50 2.5V LVPECL Driver VCCO = 2.5V 2.5V 50 50
might require a slight adjustment to optimize the frequency accuracy. will require adjusting C1 and C2. power supplies to isolate noise from coupling into the internal PLL. Figure 6. 843071 Application Schematic
This section provides information on power dissipation and junction temperature for the 843071. Equations and example calculations are also provided. The total power dissipation for the 843071 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC= 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Table 6. Thermal Resistance JA for 8 Lead TSSOP , Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP
FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 16 REVISION C 10/19/15
Ordering Information
Table 9. Ordering Information
REVISION C 10/19/15 17 FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Rev Table Page Description of Change Date B T3C 2.5V Power Supply Table - Changed 2.5V±10% to 2.5V±5%. Corrected 2.5V throughout the datasheet. Crystal Input Interface - changed C1/C2 capacitor values from 22p/22p to 27p/33p. Added L VCMOS to XT AL Interface section. Ordering Information Table - corrected standard marking from 3071A to 071AI. 6/11/07 B T3D T5A, T5B LVPECL DC Characteristics Table - corrected V OH/VOL parameters from “Current” to “Voltage” and units from "µA" to "V". AC Characteristics Table - added thermal note. Updated text in Power Supply Filtering Techniques section. Updated “Overdriving the Crystal Interface” section. Updated header/footer. 10/13/10 B 12 Added schematic 11/9/12 C Updated header/footer throughout the datasheet. Deleted IDT prefix and “I” suffix from part number. Features Section - deleted leaded information in the last bullet. Added outline box around Block Diagram. Updated Overdriving the XT AL Interface application note. Ordering Information table - deleted leaded parts rows and note. 10/19/15
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