843034EY-06LF

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FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET 843034-06 REVISION B 8/17/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843034-06 is a general purpose, low phase noise LVPECL synthesizer which can generate frequencies for a wide variety of applications. The 843034-06 has a 4:1 input multiplexer from which the following inputs can be selected: one differential input, one single-ended input, or one of two crystal oscillators, thus making the device ideal for frequency translation or frequency generation. The 843034-06 has dual LVPECL outputs that may be programmed for ÷2, ÷4 or ÷5 of the VCO frequency. The 843034-06 also supplies a buffered copy of the reference clock or crystal frequency on the single-ended REF_OUT pin which can be enabled or disabled (disabled by default). The output frequency can be programmed using either a serial or parallel programming interface. This device supports Spread Spectrum Clocking (SSC) for EMI reduction.

FEATURES

• Dual differential 3.3V LVPECL outputs
• 4:1 Input Mux: One differential input One single-ended input Two crystal oscillator interfaces
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 120MHz to 375MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 600MHz to 750MHz
• Supports Spread Spectrum Clocking (SSC)
• Parallel or serial interface for programming feedback divider and output dividers
• RMS phase jitter at 166.6MHz, using a 22.222MHz crystal (12kHz to 30MHz): 1.33ps (typical), SSC - Off
• 3.3V supply mode
• 0°C to 75°C ambient operating temperature
• Available in lead-free (RoHS 6) package PIN ASSIGNMENT OSC ÷ M 011 100 001 2÷ OSC VCO OE_A OE_B MR VCO_SEL CLK nCLK SEL1 SEL0 REF_CLK OE_REF S_LOAD S_DATA S_CLOCK nP_LOAD M8:M0 NA2:NA0 XTAL_IN0 XTAL_OUT0 XTAL_IN1 XTAL_OUT1 FOUTA0 nFOUTA0 FOUTB0 nFOUTB0 REF_OUT TEST V CCO_REF VCCO_B VCCO_A Pullup/Pulldown Pullup Pullup Pullup Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Configuration Interface Logic Phase Detector NA2 Pulldown, NA1:0 Pullup M0:M4 M6:M8 Pulldown, M5 Pullup BLOCK DIAGRAM

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

2 REVISION B 8/17/15

will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defi ned as follows: The M value and the required values of M0 through M8 are shown in Table 4B to program the VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 22.22MHz reference are defi ned as 26 ≤ M ≤ 33. The frequency out is defi ned as follows: Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and NA output divider when S_LOAD tran- sitions from LOW-to-HIGH. The M divide and NA output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and NA output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and NA bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 22.22MHz crystal. Valid PLL loop divider values for differ- ent crystal or input frequencies are defi ned in the Input Frequency Characteristics, Table 6, NOTE 1. The 843034-06 features a fully integrated PLL and therefore requires no external components for setting the loop band- width. A fundamental crystal is used as the input to the on- chip oscillator. The output of the oscillator is fed into the phase detector. A 22.22MHz crystal provides a 22.22MHz phase detector reference frequency. The VCO of the PLL operates over a range of 600MHz to 750MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The 843034-06 supports either serial or parallel programming modes to program the M feedback divider and N output divider. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on the M and NA inputs are passed directly to the M divider and N output dividers. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M and N dividers remain loaded until the next LOW transition on nP_LOAD or until a serial event oc- curs. As a result, the M and NA bits can be hardwired to set the M divider and NA output divider to a specifi c default state that T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Output 1 0 Output of M divider 1 1 Same frequency as FOUTA0 fVCO = fxtal x M FOUT = fVCO = fxtal x M N N

TABLE 1. SSM OPERATION which places the 843034-06 in the mode of spread spectrum off. M >31 when using center spread. a relock to the new input frequency.

4 REVISION B 8/17/15

TABLE 2. PIN DESCRIPTIONS input. LVCMOS/LVTTL interface levels. 2, 3, 4 RESERVED Reserve Reserved pins. Do not connect. 5 OE_REF Input Pulldown Output enable. Controls enabling and disabling of REF_OUT output. LVCMOS/LVTTL interface levels. outputs. LVCMOS/LVTTL interface levels. outputs. LVCMOS/LVTTL interface levels.

13 TEST Output

Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. TA0 Output Differential output for the synthesizer. LVPECL interface levels. Power Output supply pin for FOUTA0, nFOUTA0. nFOUTB0 Output Differential output for the synthesizer. LVPECL interface levels. Power Output supply pin for FOUTB0, nFOUTB0. 21 REF_OUT Output Reference clock output. LVCMOS/LVTTL interface levels. Power Output supply pin for REF_OUT output.

25 MR Input Pulldown

26 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on

the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. of S_CLOCK. LVCMOS/LVTTL interface levels. 30, 31 SEL0, SEL1 Input Pulldown Clock select inputs. LVCMOS/LVTTL interface levels. 32 REF_CLK Input Pulldown Reference clock input. LVCMOS/LVTTL interface levels.

TABLE 3. PIN CHARACTERISTICS TABLE 2. PIN DESCRIPTIONS, CONTINUED 37 CLK Input Pulldown Non-inverting differential clock input. /2 default when left fl oating. dividers. LVCMOS/LVTTL interface levels. 40 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS/LVTTL interface levels. 46 M5 Input Pullup M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

6 REVISION B 8/17/15

TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset the PLL. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LH X XL ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LH X X ↑ L Data Contents of the shift register are passed to the M divider and N output divider. LH X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LH X X H ↑ Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 6 0 0 2 7 000011010 666.6 30 000011110 711.04 (default) 32 000100000 733.3 33 000100001 NOTE 1: These M divide values and the resulting frequencies correspond to crystal, CLK, or REF_CLK input frequency of 22.22MHz. Inputs N Divider Value Output Frequency (MHz) *NA2 *NA1 *NA0 Minimum Maximum 0 0 1 2 300 375 0 1 1 4 150 187.5 (default) 1 0 0 5 120 150 *NOTE: Programming for Bank A and Bank B.

7 FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO_A = V CCO_B = V CCO_REF = 3.3V±5%, V EE = 0V, TA = 0°C TO 75°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, V O (LVCMOS) -0.5V to V CCO + 0.5V Outputs, I O (LVPECL) Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 65.7°C/W (0 mps) Stor age Temperature, T STG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.17 3.3 V CC V V CCO_A, V CCO_B, V CCO_REF Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 173 mA I CCA Analog Supply Current 17 mA TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, V CC = V CCO_REF = 3.3V±5%, V EE = 0V, TA = 0°C TO 75°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current REF_CLK, MR, SEL[1:0], OE_REF, S_CLOCK, S_DATA, S_LOAD, nP_LOAD, NA2, M1:M4, M6:M8 V CC = V IN = 3.465V 150 µA OE_A, M5, OE_B, VCO_SEL, NA0, NA1 V CC = V IN = 3.465V 5 µA I IL Input Low Current REF_CLK, MR, SEL[1:0], OE_REF, S_CLOCK, S_DATA, S_LOAD, nP_LOAD, NA2, M1:M4, M6:M8 V CC = 3.465V, V IN = 0V -5 µA OE_A, M5, OE_B, VCO_SEL, NA0, NA1 V CC = 3.465V, V IN = 0V -150 µA V OH Output High Voltage TEST; NOTE 1 V CCO_REF = 3.3V±5% 2.6 V REF_OUT V CCO_REF - 0.3V V V OL Output Low Voltage TEST; NOTE 1 V CCO_REF = 3.3V±5% 0.5 V REF_OUT 0.4 V NOTE 1: Outputs terminated with 50Ω to V CCO_REF /2. See Parameter Measurement Information Section, “Output Load Test Circuit Diagrams.

8 REVISION B 8/17/15

should not be less than -0.3V. TABLE 6. INPUT FREQUENCY CHARACTERISTICS, V TABLE 7. CRYSTAL CHARACTERISTICS maximum frequency of 40MHz, valid values of M are 15 ≤ M ≤ 18.

TABLE 8. AC CHARACTERISTICS, V NOTE: Characterized using a 22.22MHz crystal producing a VCO frequency of 666.66MHz, unless otherwise noted. NOTE: See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Characterized with REF_OUT output disabled. NOTE 3: Jitter performance using XTAL inputs. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 5: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points.

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

10 REVISION B 8/17/15

TYPICAL PHASE NOISE AT 166.6MHZ 166.6MHz RMS Phase Jitter (Random) 12kHz to 30MHz = 1.33ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Filter Raw Phase Noise Data Phase Noise Result by adding a Filter to raw data

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

11 REVISION B 8/17/15

PARAMETER MEASUREMENT INFORMATION 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW DIFFERENTIAL INPUT LEVELS OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD CYCLE-TO-CYCLE JITTER

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

13 REVISION B 8/17/15

FIGURE 4C. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4B. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 4D. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. FIGURE 4A. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 4A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK FIGURE 4E. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V FIGURE 4F. H IPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

15 REVISION B 8/17/15

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used FIGURE 7B. LVPECL OUTPUT TERMINATIONFIGURE 7A. LVPECL OUTPUT TERMINATION to maximize operating frequency and minimize signal distortion. Figures 7A and 7B show two different layouts which are recom- mended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock com- ponent process variations. TERMINATION FOR 3.3V LVPECL OUTPUTS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. CLK/nCLK I NPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. REF_CLK I NPUT For applications not requiring the use of the reference clock, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS C ONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUTS The unused LVCMOS output can be left fl oating. We recommend that there is no trace attached. LVPECL O UTPUTS All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated. 84 84 3.3VR3 125 125 Z o = 50 Zo = 50 Input 3.3V 3.3V

16 FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer APPLICATION SCHEMATIC EXAMPLE Figure 8 shows an example of 843034-06 application schematic. In this example, the device is operated at V CC CCO = 3.3V. The device are be driven by a crystal, LVCMOS or LVPECL input sources. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different F IGURE 8. 843034-06 APPLICATION SCHEMATIC EXAMPLE board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. For the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note 10u NA0 VCC VCC V CCO=3.3V OE_REF R10 27pF Zo = 50 Ohm VCC VCCA VCC Zo = 50 Ohm Driver_LVPECL 0.01u RU2 Not Install 133 R13 Zo = 50 Ohm 133 3.3V 0.1u VCCO 133 nFOUTB0 Zo = 50 Ohm Set Logic Input to '0' VCC VCC Logic Control Input Examples VCCO 133 VCO_SEL FOUTB0 FOUTB0 To Logic Input pins FOUTA0 3.3V 82.5 R12 REF_OUT Zo = 50 Ohm 82.5 27pF OE_A RESERVED RESERVED RESERVED OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE TEST VCC FOUTA0 nFOUTA0 VCCO_A FOUTB0 nFOUTB0 VCCO_B REF_OUT VCCO_REF nc VEE XTAL_OUT1 XTAL_IN1 XTAL_OUT0 XTAL_IN0 REF_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK MR VCO_SEL nP_LOAD nCLK CLK 18pF nFOUTA0 NA2 0.1u LVCMOS nFOUTB0 To Logic Input pins VCC 0.1u Zo = 50 Ohm SEL0 SEL1 82.5 FOUTA0 RD2 0.1u OE_B 0.1u VCCO MR Optional Y-Termination 82.5 Zo = 50 Ohm R11 VCC=3.3V NA1 nFOUTA0 LVPECL VCC RD1 Not Install RU1 X125MHz Set Logic Input to '1'

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

17 REVISION B 8/17/15

This section provides information on power dissipation and junction temperature for the 843034-06. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843034-06 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Core and LVPECL Output Power Dissipation

• Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 173mA = 599.45mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW LVCMOS Output Power Dissipation
• Output Impedance R OUT Power Dissipation due to Loading 50Ω to V CCO_REF Output Current I OUT = V CCO_MAX / [2 * (50Ω + R OUT
• Power Dissipation on the R OUT per LVCMOS output Power (R OUT ) = R OUT * (I OUT = 7Ω * (30.4mA) = 6.97mW per output Total Power Dissipation
• Total Power = Power (LVPECL) + Power (R OUT = 599.45mW + 60mW + 6.47mW = 665.92mW

the device. The maximum recommended junction temperature for devices is 125°C. and a multi-layer board, the appropriate value is 65.7°C/W per Table 9 below. and the type of board (single layer or multi-layer). TABLE 9. THERMAL RESISTANCE θJA FOR 48-PIN LQFP, FORCED CONVECTION

19 REVISION B 8/17/15

1. Calculations and Equations.

pose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 9. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 10. θ

21 REVISION B 8/17/15

TABLE 11. PACKAGE DIMENSIONS

TABLE 12. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer 843034-06 DATA SHEET

23 REVISION B 8/17/15

Rev Table Page Description of Change Date A 8 16 Added Applications Schematic. 11/19/08 B T4B T4C Features Section - changed min. VCO from 560MHz to 600MHz. Programmable VCO Frequency Table - changed fi rst row VCO frequency from 577.7 to 600 and M Divide from 26 to 27. Programmable Output Divider Table - change Output Frequency Minimum columns from (1st row) 280 to 300; (2nd row) 140 to 150; (3rd row) 112 to 120. Input Frequency Characteristics - changed VCO min. from 560MHz to 600MHz. Change min. input frequency value from 47 to 50, changed max. value from 14 to 15. AC Characteristics Table - changed min. output frequency from 112MHz to 120MHz. 8/10/09 B Product Discontinuation Notice - Last time buy expires August 14, 2016. PDN CQ-15-04 Updated data sheet format. 8/17/15

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