843031I-01 RENESAS | Alldatasheet

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  • Manufacturer or author: rdvorak
  • PDF pages: 17

Technical content

Crystal-to-3.3V, 2.5V LVPECL Clock Generator 843031I-01 DATA SHEET 843031I-01 REVISION A 10/15/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843031I-01 is an 10Gb Ethernet Clock Generator. The 843031I-01 uses an 18pF parallel resonant crystal. The 843031I-01 has excellent <1ps phase jitter performance, over the 1.875MHz - 20MHz integration range. The 843031I-01 is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.

FEATURES

  • One differential 3.3V or 2.5V LVPECL output
  • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal
  • Output frequencies: 280MHz – 340MHz
  • VCO range: 560MHz - 680MHz
  • RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.46ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 843031I-01 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ OE BLOCK DIAGRAM XTAL_IN XTAL_OUT Q nQ COMMON CONFIGURATION TABLE PIN ASSIGNMENT OE Pullup OSC Phase Detector VCO M = ÷25 (fixed) N = ÷2 (fixed) Inputs Output Frequency (MHz)Crystal Frequency (MHz) M N Multiplication Value M/N 25 25 2 12.5 312.5

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TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 5 OE Input Pullup Output Enable pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

0 Hi-Z

1 Enabled

TABLE 3. OE FUNCTION TABLE

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3.3V, 2.5V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 101.7°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, V CC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V CC Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Power Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.12 3.3 3.465 V I CCA Analog Supply Current 12 mA I EE Power Supply Current 105 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Power Supply Voltage 2.375 2.5 2.625 V V CCA Analog Supply Voltage V CC – 0.12 2.5 2.625 V I CCA Analog Supply Current 12 mA I EE Power Supply Current 90 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V CC = 3.3V 2 V CC + 0.3 V V CC = 2.5V 1.7 V CC + 0.3 V V IL Input Low Voltage V CC = 3.3V -0.3 0.8 V V CC = 2.5V -0.3 0.7 V I IH Input High Current V CC = V IN = 3.465V or 2.625V 5 µA I IL Input Low Current V CC = 3.465V or 2.625V, V IN = 0V -150 µA

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TABLE 5. CRYSTAL CHARACTERISTICS specifi cations after thermal equilibrium has been reached under these conditons. NOTE 1: Please refer to the Phase Noise Plots following this section. specifi cations after thermal equilibrium has been reached under these conditons. NOTE 1: Please refer to the Phase Noise Plots following this section. NOTE: It is not recommended to overdrive the crystal input with an external clock.

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3.3V, 2.5V LVPECL CLOCK GENERATOR 10Gb Ethernet Filter Raw Phase Noise Data Phase Noise result by adding 10Gb Ethernet Filter to raw data 100 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1K 10K 100K 1M 10M 100M TYPICAL PHASE NOISE AT 312.5MHZ AT 3.3V 312.5MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.46ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER

3.3V, 2.5V LVPECL CLOCK GENERATOR 843031I-01 DATA SHEET

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PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME

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3.3V, 2.5V LVPECL CLOCK GENERATOR

APPLICATION INFORMATION

FIGURE 2. CRYSTAL INPUt INTERFACE resonant crystal and were chosen to minimize the ppm error. FIGURE 1. POWER SUPPLY FILTERING

3.3V, 2.5V LVPECL CLOCK GENERATOR 843031I-01 DATA SHEET

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TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.

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3.3V, 2.5V LVPECL CLOCK GENERATOR TERMINATION FOR 2.5V LVPECL OUTPUTS Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to V CC - 2V. For V CC = 2.5V, the V CC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLEFIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 Zo = 50 Ohm 250 2.5V 2,5V LVPECL Driver 62.5 250 Zo = 50 Ohm 2.5V VCC=2.5V Zo = 50 Ohm Zo = 50 Ohm 2,5V LVPECL Driver VCC=2.5V 2.5V 2,5V LVPECL Driver VCC=2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm

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This section provides information on power dissipation and junction temperature for the 843031I-01. Equations and example calculations are also provided. The total power dissipation for the 843031I-01 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 105mA = 363.8mW
  • Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

TABLE 7. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION

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  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

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TABLE 8. θ

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TABLE 9. PACKAGE DIMENSIONS

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TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

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3.3V, 2.5V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page Description of Change Date A T3 2 Added OE Function Table. 1/23/07 A T10 Common Confi guration Table - corrected typo in Multiplication Value M/N column from 25 to 12.5. Ordering Information Table - added lead-free marking. 11/11/08 A T5 T10 Deleted HiPerClockS references. Crystal Characteristics Table - added note. Deleted application note, LVCMOS to XTAL Interface. Deleted quantity from tape and reel. 10/22/12 Updated data sheet format. 10/15/15

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