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Crystal-to-3.3V LVPECL Frequency Synthesizer 8430252-45 DATASHEET 8430252-45 REVISION A 5/27/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 8430252-45 is a 2 output LVPECL and LVCMOS/LVTTL Synthesizer optimized to generate Ethernet reference clock frequencies . Using a 25MHz, 18pF parallel resonant crystal, the following fre-quencies can be generated: 156.25MHz LVPECL output and, 125MHz LVCMOS output. The 8430252-45 uses IDT’s rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 8430252-45 is packaged in a small 16-pin TSSOP package.
FEATURES
One differential 3.3V LVPECL output and One LVCMOS/LVTTL output Crystal oscillator interface designed for a 25MHz, 18pF parallel resonant crystal A 25MHz crystal generates both an output frequency of 156.25MHz (LVPECL) and 125MHz (LVCMOS) VCO frequency: 625MHz RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz) using a 25MHz crystal: 0.39ps (typical) Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM XTAL_IN XTAL_OUT QA QB nQB PIN ASSIGNMENT OSC Phase Detector VCO 625MHz Feedback Divider ÷25 ÷525MHz CLK_EN OE Pullup Pullup OE VEE QA VCCO_A nc nc V CCA VCC CLK_EN V EE QB nQB V CCO_B XTAL_IN XTAL_OUT V EE 8430252-45 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS
0 Hi-Z
1 Active
0 Low High
1 Active Active
1 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. See Table 3A Function Table. 3 QA Output LVCMOS/LVTTL clock output. Power Output supply pin for QA output. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Power Output supply pin for QB, nQB outputs. 13, 14 nQB, QB Output Differential clock outputs. LVPECL interface levels. 16 CLK_EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3B Function Table.
FemtoClock® Crystal-to- 3.3V LVPECL Frequency Synthesizer 8430252-45 DATA SHEET
3 REVISION A 5/27/15
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCA = V CCO_A, V CCO_B = 3.3V±5%, TA = 0°C TO 70°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCA = V CCO_A = 3.3V±5%, TA = 0°C TO 70°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 89°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current OE, CLK_EN V CC = V IN = 3.465V 5 I IL Input Low Current OE, CLK_EN V CC = 3.465V, V IN = 0V -150 V OH Output High Voltage; NOTE 1 2.6 V V OL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to V CCO_A /2. See Parameter Measurement Information Section, “3.3V Output Load Test Circuit”. TABLE 4C. LVPECL DC CHARACTERISTICS, V CC = V CCA = V CCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V OH Output High Voltage; NOTE 1 V CCO_B - 1.4 V CCO_B - 0.9 V V OL Output Low Voltage; NOTE 1 V CCO_B - 2.0 V CCO_B - 1.7 V V SWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to V CCO_B - 2V. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.10 3.3 V CC V V CCO_A, V CCO_B Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 95 mA I CCA Analog Supply Current 10 mA
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TABLE 6. AC CHARACTERISTICS, V TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal.
125 MHz
specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the Phase Noise Plots.
FemtoClock® Crystal-to- 3.3V LVPECL Frequency Synthesizer 8430252-45 DATA SHEET
5 REVISION A 5/27/15
156.25MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.39ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 156.25MHZ 125MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.41ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 125MHZ 10Gb Ethernet Filter Phase Noise Result by adding 10Gb Ethernet Filterto raw data Raw Phase Noise Data Phase Noise Result by adding 10Gb Ethernet Filterto raw data Raw Phase Noise Data 10Gb Ethernet Filter
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3.3V LVPECL Frequency Synthesizer PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER 3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVPECL OUTPUT RISE/FALL TIME LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVCMOS OUTPUT RISE/FALL TIME
FemtoClock® Crystal-to- 3.3V LVPECL Frequency Synthesizer 8430252-45 DATA SHEET
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APPLICATION INFORMATION
The 8430252-45 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2. CRYSTAL INPUt INTERFACE resonant crystal and were chosen to minimize the ppm error. FIGURE 1. POWER SUPPLY FILTERING resistance is not required but can be added for additional protection. pair should either be left fl oating or terminated.
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3.3V LVPECL Frequency Synthesizer OVER-DRIVING THE CRYSTAL INTERFACE The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left fl oating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This confi guration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the trans- mission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and changing R2 to 50Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recom- mended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifi cations are characterized and guaranteed by using a quartz crystal as the input. FIGURE 3A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE FIGURE 3B. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE XTAL_OUT XTAL_IN Zo = 50 ohms C2 .1uf LVPECL Driv er Zo = 50 ohms 50R3 VCC XTAL_OUT XTAL_IN 100 100 Zo = 50 ohmsRsRo Zo = Ro + Rs .1uf LVCMOS Driver
FemtoClock® Crystal-to- 3.3V LVPECL Frequency Synthesizer 8430252-45 DATA SHEET
9 REVISION A 5/27/15
TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recom- mended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock com- ponent process variations. 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
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approaches are shown in the LVPECL Termination Application Note. FIGURE 5. 8430252-45 SCHEMATIC EXAMPLE
11 REVISION A 5/27/15
This section provides information on power dissipation and junction temperature for the 8430252-45. Equations and example calculations are also provided. The total power dissipation for the 8430252-45 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 95mA = 329.17mW (95mA includes the LVCMOS output terminated with 50Ω to V CC /2 at 125MHz)
- Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.465V, with all outputs switching) = 329.17mW + 30mW = 359.17mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
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TABLE 8. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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TABLE 9. PACKAGE DIMENSIONS
15 REVISION A 5/27/15
TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
FemtoClock® Crystal-to- 3.3V LVPECL Frequency Synthesizer 8430252-45 DATA SHEET
16 REVISION A 5/27/15
Rev Table Page Description of Change Date A 9 Added Schematic Layout and Guideline. 10/4/06 A T10 General Description - deleted HiperClocks logo and text reference. AC Characteristics Table - added thermal note. Updated Over-Driving the Crystal Interface section. Termination for 3.3V LVPECL Outputs - updated Figures 4A and 4B. Ordering Information Table - deleted ICS prefi x in Part/Order column. And delet- ed tape & reel count in Shipping Packaging column. 2/19/14 A T10 15 Updated data sheet format. Ordering Information - removed leaded devices. 5/27/15
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