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Crystal-to-3.3V, 2.5V LVPECL Clock Synthesizer 843022I-48 DATA SHEET 843022I-48 REVISION A 9/25/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843022I-48 is a Fibre Channel Clock Generator. The 843022I-48 uses a 25MHz crystal to synthesize 125MHz or 75MHz. The 843022I-48 has excellent phase jitter perform-ance, over the 12kHz – 20MHz integration range. The 843022I-48 is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.
FEATURES
- One differential 3.3V or 2.5V LVPECL output
- Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal
- Output frequencies: 125MHz or 75MHz (selectable)
- RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz - 20MHz): 0.72ps (typical) @ 3.3V
- Full 3.3V and 2.5V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package 843022I-48 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ FREQ_SEL OSC PLL DIV. N ÷4, ÷8 0 = ÷20 (default) 1 = ÷24 XTAL_IN XTAL_OUT FREQ_SEL Q nQ Pulldown BLOCK DIAGRAM P IN ASSIGNMENT FUNCTION TABLE Inputs Output Frequencies (with a 25MHz crystal)FREQ_SEL M Divide N Divide 0 ÷20 ÷4 125MHz (default) 1 ÷24 ÷8 75MHz
2 REVISION A 9/25/15
TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 5 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential clock output. LVPECL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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3.3V, 2.5V LVPECL CLOCK GENERATOR TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 101.7°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, V CC = V CCA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 1.3 V CC + 0.3 V V IL Input Low Voltage -0.3 0.7 V I IH Input High Current V CC = V IN = 3.465V 150 µA I IL Input Low Current V CC = 3.465V, V IN = 0V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.10 3.3 V CC V I CCA Analog Supply Current 10 mA I EE Power Supply Current 80 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 2.375 2.5 2.625 V V CCA Analog Supply Voltage V CC – 0.10 2.5 V CC V I CCA Analog Supply Current 10 V I EE Power Supply Current 75 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 1.1 V CC + 0.3 V V IL Input Low Voltage -0.3 0.5 V I IH Input High Current V CC = V IN = 2.625V 150 µA I IL Input Low Current V CC = 2.625V, V IN = 0V -5 µA TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, V CC = V CCA
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125 MHz
75 MHz
NOTE 1: Please refer to the Phase Noise Plot. TABLE 4. CRYSTAL CHARACTERISTICS NOTE 1: Please refer to the Phase Noise Plot. NOTE: It is not recommended to overdrive the crystal input with an external clock.
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3.3V, 2.5V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 75MHZ @ 3.3V OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter 75MHz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.51ps (typical) TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 125MHz RMS Phase Noise Jitter 12kHz to 20MHz = 0.72ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER ➤ Phase Noise Result by adding a Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR 843022I-48 DATA SHEET
6 REVISION A 9/25/15
PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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3.3V, 2.5V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE values can be slightly adjusted for different board layouts. FIGURE 1. POWER SUPPLY FILTERING
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V, 2.5V LVPECL CLOCK GENERATOR 843022I-48 DATA SHEET
8 REVISION A 9/25/15
TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, ter- minating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
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3.3V, 2.5V LVPECL CLOCK GENERATOR TERMINATION FOR 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to V CC - 2V. For V CC = 2.5V, the V CC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLEFIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 Zo = 50 Ohm 250 2.5V 2,5V LVPECL Driver 62.5 250 Zo = 50 Ohm 2.5V VCC=2.5V Zo = 50 Ohm Zo = 50 Ohm 2,5V LVPECL Driver VCC=2.5V 2.5V 2,5V LVPECL Driver VCC=2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm
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This section provides information on power dissipation and junction temperature for the 843022I-48. Equations and example calculations are also provided. The total power dissipation for the 843022I-48 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 80mA = 277.2mW
- Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.465V, with all outputs switching) = 277.2mW + 30mW = 307.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
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- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
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TABLE 7. θ
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TABLE 8. PACKAGE DIMENSIONS
14 REVISION A 9/25/15
TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
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3.3V, 2.5V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page Description of Change Date A T4 Deleted HiPerClocks references. Crystal Characteristics Table - added note. Deleted application note, LVCMOS to XTAL Interface. Deleted quantity from tape and reel 9/22/12 Updated data sheet format. 9/25/15
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