843021I-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: rdvorak
  • PDF pages: 17

Technical content

Features

  • One differential 3.3V or 2.5V LVPECL output
  • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal
  • Output frequency range: 125MHz, using a 25MHz crystal
  • VCO range: 490MHz – 640MHz
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.41ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 843021I-01

8 Lead TSSOP

4.40mm x 3.0mm x 0.925mm package body G Package Top View Pin Assignment VCC XTAL_OUT XTAL_IN VEE Q nQ VCC OE Block Diagram OSC Phase Detector VCO ÷4 (fixed) ÷20 (fixed) Q nQ XTAL_IN XTAL_OUT OE Pullup 25MHz

843021I-01 Rev A 9/25/15 2 ©2015 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1, 6 V CC Power Power supply pins. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 4V EE Power Negative supply pin.

5 OE Input Pullup

Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and are in a high impedance state. LVCMOS/LVTTL interface levels. 7, 8 nQ, Q Output Differential output pair. LVPECL interface levels.

843021I-01 Rev A 9/25/15 3 ©2015 Integrated Device Technology, Inc. NOTE 1: Outputs termination with 50 to VCC – 2V. NOTE 1: Outputs termination with 50 to VCC – 2V. Table 4. Crystal Characteristics

843021I-01 Rev A 9/25/15 4 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Table 5A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Please refer to Phase Noise Plot. Table 5B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Please refer to Phase Noise Plot. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 122.5 125 160 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 125MHz, ( Integration Range: 1.875MHz – 20MHz) 0.41 ps tR / tF Output Rise/Fall Time 20% to 80% 250 600 ps odc Output Duty Cycle 49 51 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 122.5 125 160 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 125MHz, ( Integration Range: 1.875MHz – 20MHz) 0.42 ps tR / tF Output Rise/Fall Time 20% to 80% 250 600 ps odc Output Duty Cycle 49 51 %

843021I-01 Rev A 9/25/15 5 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Typical Phase Noise at 125MHz (3.3V or 2.5V) Gigabit Ethernet Filter Phase Noise Result by adding a Gigabit Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz (3.3V)= 0.41ps (typical) 1.875MHz to 20MHz (2.5V)= 0.42ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

843021I-01 Rev A 9/25/15 6 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter 2.5V LVPECL Output Load AC Test Circuit Output Rise/Fall Time SCOPE Qx nQx VEE VCC -1.3V ± 0.165V Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ Q SCOPE Qx nQx VEE VCC -0.5V ± 0.125V nQ Q Output Duty Cycle/Pulse Width/Period

843021I-01 Rev A 9/25/15 8 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

843021I-01 Rev A 9/25/15 11 ©2015 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the 843021I-01. Equations and example calculations are also provided. The total power dissipation for the 843021I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection

843021I-01 Rev A 9/25/15 12 ©2015 Integrated Device Technology, Inc.

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

843021I-01 Rev A 9/25/15 13 ©2015 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP

843021I-01 Rev A 9/25/15 14 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

843021I-01 Rev A 9/25/15 15 ©2015 Integrated Device Technology, Inc. 843021I-01 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date A T1 2 Pin Description Table - corrected typo in V CC row, pins 1, 6 instead of 1, 8. 11/10/08 A T3D - T3E 3 LVPECL DC Characteristics Tables - corrected VOH/VOL parameters from “Current” to “Voltage” and units from “uA” to “V”. Updated “Overdriving the Crystal Interface” section. Updated header/footer. 10/15/10

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