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Document overview
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- PDF pages: 15
Technical content
Features
- One differential 3.3V LVPECL output
- Crystal oscillator interface designed for 22.4MHz – 28MHz, 18pF parallel resonant crystal
- Output frequency range: 112MHz – 140MHz
- VCO range: 560MHz – 700MHz
- Output duty cycle range: 49% – 51%
- RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.650ps (typical) Offset Noise Power
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- Industrial temperature information available upon request
Table 1. Frequency Table - Typical Applications
8 Lead TSSOP
843021 DATA SHEET
Table 2. Pin Descriptions Table 3. Pin Characteristics NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1V CCA Unused Analog supply pin. 2V EE Power Negative supply pin. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 6, 7 nQ0, Q0 Output Differ ential output pair. LVPECL interface levels. 8V CC Power Core supply pin.
NOTE 1: Outputs termination with 50 to VCC – 2V. Table 5. Crystal Characteristics NOTE 1:Input frequency is limited to a range of 22.4MHz – 28MHz due to VCO range. Table 6. AC Characteristics, VCC = 3.3V ± 10%, VEE = 0V, TA = 0°C to 70° has been reached under these conditions. NOTE 1: Refer to Phase Noise Plot.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 4 Rev D 9/25/15 Typical Phase Noise at 125MHz Noise Power dBc Hz Offset Frequency (Hz) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 5 Rev D 9/25/15 Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period RMS Phase Jitter Output Rise/Fall Time SCOPE Q nQ LVPECL VEE VCC, VCCA -1.3V±0.33V nQ0 Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ0
Figure 1. Power Supply Filtering values can be slightly adjusted for different board layouts. Figure 2. Crystal Input Interface
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 7 Rev D 9/25/15 Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface 100 100RS 43 Ro ~ 7 Ohm Driver_LVCMOS Zo = 50 Ohm C1 0.1uF 3.3V 3.3V Crystal Input Interface XTAL_I N XTAL_OU T Crystal Input Interface XTAL_IN XTAL_OUT 0.1uF Zo = 50 Ohm LVPECL Zo = 50 Ohm VCC=3.3V
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 8 Rev D 9/25/15 Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
example of LVPECL termination is shown in this schematic. values may be slightly adjusted for optimizing frequency accuracy. Figure 5. 843021 Schematic Example capacitors should be located as close as possible to the power pins. Table 7. Footprint Table shown in this layout example.
This section provides information on power dissipation and junction temperature for the 843021. Equations and example calculations are also provided. The total power dissipation for the 843021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 90.5°C/W per Table 8 below. Table 8. Thermal Resitance JA for 8 Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 9. JA vs. Air Flow Table for a 8 Lead TSSOP
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 13 Rev D 9/25/15
Ordering Information
Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 14 Rev D 9/25/15 Rev Table Page Description of Change Date B T5 Added Function Table. Features section - updated Crystal, Output Frequency & VCO range bullets. Crystal Characteristics Table - changed Frequency from 25MHz typical to 14MHz min. and 40MHz max. Added Note 1. AC Characteristics Table - changed Output Frequency from 125MHz typical to 112MHz min. and 140MHz max. 10/6/04 C T4A 3 Power Supply Table - increased V CC to 3.3V ± 10% from 5% and is reflected throughout the datasheet. 11/3/04 C T8 T11 Absolute Maximum Ratings - corrected Package Thermal Impedance air flow. Thermal Resistance Table - corrected air flow. Corrected air flow in table. Ordering Information Table - corrected marking. 11/30/04 C T11 Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free part number. 3/31/05 D Features section - changed RMS phase jitter spec. AC Characteristics Table - added maximum RMS Phase Jitter spec of 0.65ps. Added LVCMOS to XTAL Interface section. Added Termination for 3.3V LVPECL Output section. Updated datasheet to new format. 11/21/07 D T4B T11 LVPECL DC Characteristics Table - corrected V OH/VOL parameters from “Current” to “Voltage” and units from “uA” to “V”. AC Characteristics Table - added thermal note. Updated text in “Power Supply Filtering Techniques”. Updated “Overdriving the Crystal Interface” section. Ordering Information Table - deleted “ICS” prefix for part/order column. Updated header/footer. 10/12/10 Updated data sheet format. 9/25/15
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