ICS843021I IDT | Alldatasheet
Document overview
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Technical content
Features
- One differential 3.3V LVPECL output
- Crystal oscillator interface designed for 22.4MHz – 28MHz, 18pF parallel resonant crystal
- Output frequency range: 112MHz – 140MHz
- VCO range: 560MHz – 700MHz
- Output duty cycle range: 49% – 51%
- RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.650ps (typical) Offset Noise Power
- Full 3.3V supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
Table 1. Frequency Table - Typical Applications
8 Lead TSSOP
ICS843021AGI REVISION A MAY 18, 2011 2 ©2011 Integrated Device Technology, Inc. Table 2. Pin Descriptions Table 3. Pin Characteristics NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1V CCA Unused Analog supply pin. 2V EE Power Negative supply pin. XTAL_IN Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 6, 7 nQ0, Q0 Output Differ ential output pair. LVPECL interface levels. 8V CC Power Core supply pin.
ICS843021AGI REVISION A MAY 18, 2011 3 ©2011 Integrated Device Technology, Inc. NOTE 1: Outputs termination with 50Ω to VCC – 2V. Table 5. Crystal Characteristics NOTE 1:Input frequency is limited to a range of 22.4MHz – 28MHz due to VCO range. Table 6. AC Characteristics, VCC = 3.3V ± 10%, VEE = 0V, TA = 0°C to 70° has been reached under these conditions. NOTE 1: Refer to Phase Noise Plot.
ICS843021AGI REVISION A MAY 18, 2011 4 ©2011 Integrated Device Technology, Inc. ICS843021I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Typical Phase Noise at 125MHz Noise Power dBc Hz Offset Frequency (Hz) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
ICS843021AGI REVISION A MAY 18, 2011 5 ©2011 Integrated Device Technology, Inc. ICS843021I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period RMS Phase Jitter Output Rise/Fall Time SCOPE Q nQ LVPECL VEE VCC, VCCA -1.3V±0.33V nQ0 tPW tPERIOD tPW tPERIOD odc = x 100% Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF VSWING nQ0
ICS843021AGI REVISION A MAY 18, 2011 6 ©2011 Integrated Device Technology, Inc. values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface
ICS843021AGI REVISION A MAY 18, 2011 8 ©2011 Integrated Device Technology, Inc. ICS843021I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V
ICS843021AGI REVISION A MAY 18, 2011 10 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843021I. Equations and example calculations are also provided. The total power dissipation for the ICS843021I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 112.4°C/W per Table 7 below. Table 7. Thermal Resitance θJA for 8 Lead TSSOP, Forced Convection
ICS843021AGI REVISION A MAY 18, 2011 11 ©2011 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 5. Figure 5. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
ICS843021AGI REVISION A MAY 18, 2011 12 ©2011 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 8 Lead TSSOP
ICS843021AGI REVISION A MAY 18, 2011 13 ©2011 Integrated Device Technology, Inc. ICS843021I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.
ICS843021I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.
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